Venkata Appa Rao Yempada, Research Scholar, Center for VLSI and Embedded Systems Technology (CVEST) working under the supervision of Dr. Srivatsava Jandhyala, was awarded the best poster award for his work on Simulation study of III-V Lateral Tunnel FETs with Gate-Drain underlap at the 23rd International symposium on VLSI Design and Test (VDAT) at IIT Indore from 4 – 6 July.