Abstract
Semiconductor industry has long struggled to develop systems that operate at higher speeds, thereby
reaching giga-hertz or even tera-hertz in the recent times. However, newly emerging applications like
biomedical, environmental monitoring, surveillance etc., place contrast requirements to these high speed
systems. These applications do not require higher speeds, however they do not have access to wall power
(in most cases) and must resort to energy harvesting, miniaturized batteries, thereby placing power
consumption as the bottleneck. Additionally, systems powered through energy harvesting must be able
to work with lower supply voltages, while systems powered by miniaturized batteries must be able to
work for wide supply voltages precluding the need of voltage regulator. For biomedical applications,
these systems should also occupy lower form factor, so that they could lead to less invasive surgeries.
Temperature is one of most important sensing modality for any IoT system, and hence temperature sensor must be designed keeping the above constraints in mind. Consequently, we propose 47nW
temperature sensor in TSMC 180nm technology node and 419pW temperature sensor in UMC 55nm
technology node. Both the sensors are based on completely different architectures. In TSMC 180nm
technology, temperature is transduced to delay using temperature characteristics of resistance and capacitance. The architecture is digital friendly, since delay can be easily converted to digital code. Since
temperature to delay conversion depends mainly on passive elements, the architecture is highly resilient
to supply variations. To further push the power consumption from nano-watt to sub nano-watt regime
and reduce the area further, we exploit the temperature dependency of gate-leakage in lower technology
nodes. A process and supply-invariant proportional-to-absolute-temperature voltage (VP T AT ) is generated by using BJTs and gate leakage characteristics in UMC 55nm technology. The obtained VP T AT is
highly resilient to process and supply variations and occupies lower form factor.
Biasing circuits being common to any analog circuits, must also be designed for the above constraints. Consequently, we propose 50nA current reference in TSMC 180nm technology node and 60pA
current reference, 600mV voltage reference in UMC 55nm technology node. Both the current references
are based on completely different architectures. In TSMC 180nm technology, we design the 50nA current reference by cancelling the temperature coefficient of voltage and temperature characteristics of
resistance. A voltage bias circuit is designed in a way that the obtained current reference temperature
coefficient is independent of process variations, necessitating only single point trim. However, this architecture cannot be used for designing sub-nW currents, as it requires impracticably high resistances.
To push the power consumption of current reference for sub-nW regime without compromising on area, we exploit the temperature characteristics of gate leakage in lower technology nodes. The proposed
60pA current reference is the first sub-nW current reference that solves the problem of exponential
power consumption with temperature and process. With a slight modification to this architecture, we
develop a 600mV voltage reference for sub-nW regime. Both these sub-nW voltage and current references require only single-point trim. All the above mentioned voltage and current references work for
wide temperature range and show high supply resilience over wide supply ranges.
Sleep mode timers are essential to any duty cycled IoT nodes for synchronizing data transmission
and data reception. Although active power consumption is reduced by duty cycling, sleep mode power
consumption of timers becomes a bottleneck in scaling the overall system power consumption. These
timers are also expected to be robust to supply and temperature variations, as error in frequency necessitates additional guard band time, thereby increasing the overall system power consumption. RC
oscillators are preferred due to their excellent temperature and supply stability, However scaling power
consumption to sub-10nW, requires impracticably high resistances in the order of hundreds of mega
ohms/giga ohms. Although gate leakage in thin oxide transistors serve as effective replacements for
large resistance in lower technology nodes, TSMC 180nm does not have gate leakage and requires large
physical resistances. Consequently, we propose a resistance amplifier, a CMOS circuit that realizes the
characteristics of large resistance using small resistance, thereby saving area and hence cost. This resistance amplifier is substituted in the conventional offset compensated RC oscillator architecture, and the
overall functionality of the system is evaluated.