Abstract

This paper presents an ultra-low-power CMOS
voltage reference (VR) design that achieves very low line sen-
sitivity and a wide temperature range of operation. The core
architecture consists of only four transistors and employs a dual
regulation loop topology to enhance the line sensitivity. A gate-
source shorted PMOS serves as the main current source of
the core. An additional proportional to absolute temperature
(PTAT) generator connected to the body of the PMOS current
source to modulate Vth at subzero temperatures while bulk
diode leakage control is utilized to ensure reliable operation at
higher temperature. Simulated in a 0.18 μm CMOS process, the
proposed VR delivers a reference voltage of 451.6 mV while
consuming only 37.6 pW power. It has a line sensitivity (LS) of
0.009%/V and operates over a temperature range from -30°C to
160°C with temperature coefficient (TC) of 70.2 ppm/◦C.

Abstract

Neural approaches that rely on autoregressive (AR) solution construction for solving the Traveling Salesman Problem (TSP) - a cornerstone challenge in combinatorial optimization - can be computationally expensive during both training and inference, since each step of the solution construction requires a forward pass through the neural network. Although non-autoregressive (NAR) methods offer the promise of efficient solution generation in a single network pass, prior NAR approaches have typically depended on Monte Carlo Tree Search (MCTS) to reach near-optimal performance, which substantially slows down the solution generation and demands significant additional computational resources.

To address this, we propose NARSIL, a NAR method that generates TSP solutions extremely fast without sacrificing the solution quality. NARSIL is trained in an unsupervised manner using Self-Improvement Learning (SIL) and does not require access to optimal solutions during training.

Experimental results demonstrate that NARSIL achieves a 9-11x speed-up over the previous fastest baseline while delivering superior solution quality, and a 71-265x speed-up over high-accuracy baselines while producing comparable solution quality.

Abstract

Electronic voting systems must balance public ver-
ifiability with voter privacy and coercion resistance. Existing cryptographic protocols achieve end-to-end verifiability by revealing vote distributions, relying on trusted clients, or issuing transferable receipts. We present ACE, a voting protocol that achieves public auditability, tally-hiding, and information-theoretic receipt-freeness, assuming a single honest tallier and no client-side trust.

Abstract

This study investigates the performance, energy efficiency, and resource consumption of four agentic issue resolution frameworks (SWE-Agent, OpenHands, Mini SWE Agent, and AutoCodeRover) when constrained to Small Language Models (SLMs). Results indicate that framework architecture is the primary driver of energy consumption, but current frameworks fail to operate efficiently with SLMs, often leading to unproductive reasoning loops and low task resolution rates.

Abstract

Accurate and computationally efficient prediction of low-pressure carbon dioxide (CO2) adsorption in metal-
organic frameworks (MOFs) is essential for large-scale materials screening in carbon capture applications.
While molecular simulations such as grand canonical Monte Carlo (GCMC) yield accurate working capacity es-
timates, their high computational cost limits scalability, prompting the growing use of machine-learning-based
approaches for rapid materials discovery in recent years. Here, we present a self-supervised three-dimensional
masked autoencoder framework that learns structure-aware representations of MOFs directly from voxelized
atomic density fields. The crystal structures are mapped onto lattice-aware 3D grids that encode structural and
chemical information, enabling end-to-end learning without handcrafted features. The masked autoencoder is
pretrained by reconstructing masked voxel patches and subsequently fine-tuned with a lightweight regression
head to predict CO2 working capacity for a chemically diverse subset of the ARC-MOF database. On a held-out
test set of 12,714 structures, the model achieves high predictive accuracy and strong correlation with reference
working capacity values, with errors confined to a small subset of structurally atypical frameworks (7.8%);
for the remaining materials, predictions show near-quantitative agreement. Gradient saliency and attention
rollout show that the encoder focuses on metal-containing voxels -- the primary CO2 binding sites -- and
aligns attention with accessible pore volume, indicating physically grounded representations without explicit
labeling of adsorption sites or bond topology. The proposed pipeline enables rapid, reproducible first-stage
screening via single-component CO2 working capacity, but full PSA evaluation requires subsequent mixed-gas
adsorption, desorption thermodynamics, and selectivity analyses.

Abstract

Recent work has shown that scaling large language models (LLMs) improves their alignment with human brain activity, yet it remains unclear what drives these gains and which representational properties are responsible. Although larger models often yield better task performance and brain alignment, they are increasingly difficult to analyze mechanistically. This raises a fundamental question: what is the minimal model capacity required to capture brain-relevant representations? To address this question, we systematically investigate how constraining model scale and numerical precision affects brain alignment. We compare full-precision LLMs, small language models (SLMs), and compressed variants (quantized and pruned) by predicting fMRI responses during naturalistic language comprehension. Across model families up to 14B parameters, we find that 3B SLMs achieve brain predictivity indistinguishable from larger LLMs, whereas 1B models degrade substantially, particularly in semantic language regions. Brain alignment is remarkably robust to compression: most quantization and pruning methods preserve neural predictivity, with GPTQ as a consistent exception. Linguistic probing reveals a dissociation between task performance and brain predictivity: compression degrades discourse, syntax, and morphology, yet brain predictivity remains largely unchanged. Overall, brain alignment saturates at modest model scales and is resilient to compression, challenging common assumptions about neural scaling and motivating compact models for brain-aligned language modeling.

Abstract

This paper addresses a key challenge in Handwritten Text Recognition (HTR): the dependence on large volumes of labeled data. To overcome this, we propose a self-supervised learning (SSL) framework, LoGo-HTR, that minimizes labeling requirements while achieving strong recognition performance. We introduce a large-scale dataset, SSL-HWD of 10 million word-level handwritten images from diverse scanned documents, partitioned into a small labeled subset and a much larger unlabeled subset. LoGo-HTR combines a local contrastive loss for spatial consistency and a global decorrelation loss to enhance feature diversity. This dual objective enables robust, invariant, and spatially discriminative feature learning. After self-supervised pretraining, we fine-tune a transformer-based decoder using limited labeled data. Extensive experiments on standard HTR benchmarks, which include multilingual and historical data, demonstrate that, after SSL pretraining on our unlabeled dataset, our method consistently outperforms state-of-the-art approaches, even when fine-tuned using only 80% and 20% of the available labeled training data from the respective benchmarks. Ablation studies highlight the effectiveness of our dual loss design and demonstrate the potential of scalable, label-efficient handwritten text recognition. The SSL-HWD dataset and LoGo-HTR model with code are publicly available at https://logo-ssl.github.io/.

Abstract

Energy efficiency has emerged as a vital attribute of software quality,
with significant implications for both environmental sustainability
and operational costs. However, existing profiling tools operate
only at runtime and coarse granularity, typically capturing energy
at the process or method level. Such tools fail to expose how small
code blocks, such as functions, loops, and conditionals, contribute to
energy consumption, preventing developers from reasoning about
and comparing the energy efficiency of programming constructs
during design-time.
To address this gap, we propose EnCoDe, a methodology for
fine-grained, design-time energy estimation, with the following
key contributions: (1) PowerLens, a novel measurement method-
ology that achieves reliable sub-millisecond energy readings for
small code blocks; (2) Extensive empirical study on code blocks
extracted from over 18,000 Python programs, uncovering linear and
non-linear relationships between energy consumption and static
code features such as structural, complexity, density, and contextual
characteristics, resulting in a first-of-its-kind fine-grained dataset;
and (3) Predictive modeling, in which machine learning models
are trained on these features to accurately estimate and classify
block-level energy consumption at design-time. Our results demon-
strate stable, reproducible block-level estimations, with regressors
achieving 𝑅2 = 0.75 and classifiers achieving 80.6% accuracy in
identifying energy hotspots, enabling developers to localize and
address inefficient code regions early in the development process
without execution

Abstract

This paper presents a jitter-peaking-free, referenceless digital clock and data recovery (D-CDR) circuit implemented in a dual-loop D/PLL CDR architecture with multi-bit decimation. The design combines a DLL-based VCDL loop to suppress high-frequency jitter components, combined with a PLL-based
VCO loop for stabilizing low-frequency jitter, resulting in a
flat jitter transfer function. A multi-bit decimator losslessly
downsamples phase detector outputs, significantly reducing quantization noise and minimizing recovered clock jitter. The dualloop structure enhances loop dynamics, achieving high jitter tolerance (JTOL = 0.20 UI) and low jitter transfer (JTRAN)
without peaking with a corner frequency of 12 MHz, simulated
JTRAN BW is 7MHz. These features make the proposed D-CDR
highly suitable for high-speed serial and optical link applications.

Abstract

Hardware security in energy-constrained systems
requires highly stable primitives. This paper presents a novel weak Physical Unclonable Function (PUF) architecture implemented in a 28-nm CMOS process, leveraging mismatch-induced variations between two compact all-CMOS voltage reference circuits. The PUF response is derived from mismatch-dominated reference voltages, enabling robust entropy extraction while inherently suppressing sensitivity to environmental variations. To ensure reliable low-voltage operation at a 0.9 V nominal supply voltage, the design utilizes ultra-low threshold voltage (ULVT) devices. Simulation results for a 256-bit PUF array show
an average inter-chip uniqueness of 50.47%. Furthermore, the design demonstrates strong native stability, significantly reducing the reliance on error-correction codes and helper data overhead.
It maintains greater than 97% accuracy across a temperature range of −40◦C to 125◦C and supply voltage variations from 0.65 V to 1.1 V. This architecture provides a scalable and practical approach for hardware identification and cryptographic key generation in advanced nodes.