Abstract
As the electronics activity is penetrating into various walks of life like electronic governance, banking, reservation systems, the need for higher and higher security in protecting the banking transactions, passwords, PNR numbers, etc. is increasing. The security lapses not only occur through software but also from the hardware circuits that are used for implementing them. One of the methods of breaking the security is through the observations of the pattern of power consumed by the gadget. These methods through which the secured information is obtained are known as Side Channel Attacks (SCA). There is considerable amount of effort that is put in to make the electronic circuits immune to SCA. In this process, bulk of the effort is put in making complementary metal oxide semiconductor (CMOS) circuits immune from these attacks.
One of the normal approaches is by having a gate operated with the complementary gate in parallel, like an inverter working in parallel with a buffer, a NAND working in parallel with AND. This combination of circuits may be termed as dual-rail pre-charge (DRP) logic. Because of the additional circuits, the power consumed by the circuit in general gets doubled. So they may not be really suitable for low power applications where the battery life is also important. In view of this, the problem of reducing the power dissipation in DRP logic has been looked at.
It has been realized that adiabatic approach is a reasonable method for reducing the power dissipation. In view of this, adiabatic dual-rail inverter-buffer circuit has been built with circuit topology as shown in Figure 4.3. It has been found that this circuit works properly as an inverter, as a buffer and also results in considerable reduction in power dissipation. The current drawn from the power supply has a pattern which is independent of the input signal (0 to 1 or 1 to 0 transitions). Further it has been observed that the input and output logic levels are the same which indicates that these circuits are cascadable. In view of this, it has been concluded that it is possible to realize low power secure circuits based on adiabatic dual-rail approach.
To examine whether large scale secure systems can be built with this approach, the universal logic gates, NAND and NOR have been constructed on the lines similar to CMOS NAND, NOR with adiabatic approach. In these circuits there have been certain current patterns that emerged depending on the input signal. This difference in the pattern has been identified to be due to the number of transistors which are in the ON state are different for different input signals. This problem has been overcomed by carefully analyzing the transistors that are put ON for each of the input condition and by balancing the resistances for all the inputs. This called for incorporating additional transistors in some branches.
With this balancing technique and adiabatic approach, it has been possible to realize low power secure NAND and NOR gates. Even these gates have the same input and output logic levels which make them suitable for cascadable circuits. Thus it is clearly established that using the dual-rail adiabatic approach, secure digital circuits can be built.
Even though cascadability of the individual secure logic gates have been established, when the circuits are really cascaded, it is possible that the currents drawn may depend upon the logic functions that are executed (based on the gates that are used). To avoid this problem, the circuits have been modified to have a structure in which there is always a current drawn by each of the gates for each operation of the signal. This is done by incorporating pre-charge and evaluation steps in these circuits.
Using this approach, all the gates (Inverter-Buffer, AND-NAND, OR-NOR, XOR-XNOR) are constructed and it is observed that the current patterns are input independent and a significant amount of power reduction is observed when compared to the existing secure logic styles. Hence, low power secure logic style has been established.