Abstract

SparseLoc is a global localization framework for city-scale scenarios that leverages vision-language foundation models to generate sparse semantic topometric maps in a zero-shot manner. It combines this map representation with a Monte Carlo localization scheme enhanced by a novel late optimization strategy, ensuring improved pose estimation. By constructing compact yet highly discriminative maps and refining localization through a carefully designed optimization schedule, SparseLoc overcomes the limitations of existing topometric localization methods, offering a better solution for global localization at the scale of a city. Our system achieves over a 5× improvement in localization accuracy compared to existing sparse mapping techniques. Despite utilizing only 1/500th of the points of dense mapping methods, it achieves comparable performance, maintaining an average global localization error below 5m and 2° on KITTI Sequences.

Abstract

This paper explores advanced voltage reference designs with extremely low power consumption, specifically under one microwatt. These designs are crucial for portable electronic systems that rely on minimal power. The paper categorizes these voltage references based on the types of devices used to generate temperature-proportional or complementary signals. It also provides key design examples to illustrate these concepts. Additionally, the paper enhances understanding by conducting a comparative analysis of performance metrics, including power consumption, temperature coefficient, physical size, and resistance to variations in the manufacturing process.

Abstract

This paper presents a dual-loop reference-less Clock and Data Recovery (CDR) architecture implemented in TSMC 28nm CMOS process for PCIe Gen4 application. A novel frequency detector (FD) with a wide frequency acquisition range is presented, which avoids harmonic locking issues and is independent of input transition density. The FD demonstrates rapid locking capabilities, securing synchronization with Pseudo-Random Binary Sequences (PRBS7 and PRBS31) data patterns. The locking time from PCIe Gen1 (2.5Gbps) to PCIe Gen4 (16Gbps) is less than 5us. The CDR achieves a power consumption of less than 2mW with a supply voltage of 0.9V.

Abstract

The heightened sensitivity of circuit behavior to manufacturing processes is surging in sub-nanometer nodes, presenting a formidable challenge for high-dimensional performance modeling. Estimating circuit performance variations resulting from process randomness in upcoming technology nodes aids in implementing appropriate countermeasures to handle them. Addressing this, we introduce a multi-node transfer learning method for predicting the performance of VLSI digital circuits. The proposed method facilitates Zero-shot Learning in future technology nodes based on insights gained from analyzing the circuit’s process-induced behavior in established nodes. The approach is fast, scalable, and robust, leveraging digital standard cell characterization that can be applied to estimate the performance of a wide array of intricate circuits. Experimental results affirm the approach’s exceptional data efficiency, achieving a speed increase of up to 104 times, all the while maintaining superior accuracy compared to traditional simulators.

Abstract

Analog circuit characterization is a pivotal phase in the design process, serving to validate their performance. It ensures that design choices lead to optimization, ultimately resulting in reliable and robust designs. The conventional, resource-intensive circuit characterization using traditional simulation tools is being supplanted by Machine Learning surrogate models, providing computational advantages. Nevertheless, these models tend to be specific to particular circuits, demanding significant design efforts and often lacking reusability for other designs and topologies. In this paper, we introduce a Unified Neural Network Architecture that is versatile and computationally efficient. It offers a streamlined and effective approach for modeling a diverse array of analog circuits prone to process, voltage, and temperature variations. Experimental trials conducted on various circuits in CMOS 180nm, 65nm and 28nm technologies demonstrate a mean average percentage error of less than 1%, affirming the effectiveness and reusability of the proposed architecture. This leads to substantial savings in design time, computational resources, and characterization costs.

Abstract

Recent progress in MEMS resonant-fin-transistors (RFT) has enabled very high-Q active mode resonators, promising crystal-less monolithic clock generation for Millimeter-wave (mmWave) systems. However, there is a strong need for design of mmWave oscillators that utilize the high-Q of active-mode RFT (AM-RFT) optimally, while handling unique challenges such as resonator's low electromechanical transduction. In this brief, we develop a theory and through design and post-layout simulations in 14 nm Global Foundry (GF) process, we show the first active oscillator with AM-RFT at 30 GHz, which improves the fundamental limits of phase noise (PN) and figure-of-merit (FoM) when compared with the oscillators with conventional LC resonators. For AM-RFT with Q-factor of $sim$10k, post layout simulation results show that the proposed oscillator exhibits phase noise of less than -140 dBc/Hz and FoM greater than 228 dBc/Hz at a 1 MHz offset for 30 GHz center frequency, which are 25 dB better than the existing monolithic LC oscillators.

Abstract

We present a transformer architecture-based foundation model for tasks at high-energy particle colliders such as the Large Hadron Collider. We train the model to classify jets using a self-supervised strategy inspired by the Joint Embedding Predictive Architecture. We use the JetClass dataset containing 100M jets of various known particles to pre-train the model with a data-centric approach -- the model uses a fraction of the jet constituents as the context to predict the embeddings of the unseen target constituents. Our pre-trained model fares well with other datasets for standard classification benchmark tasks. We test our model on two additional downstream tasks: top tagging and differentiating light-quark jets from gluon jets. We also evaluate our model with task-specific metrics and baselines and compare it with state-of-the-art models in high-energy physics. Project site: this https URL

Abstract

This paper addresses the challenge of water dis- aggregation in intermediate water supply (IWS) systems using water level data. The water level node, in conjunction with four automatic labelling nodes, was deployed to collect data on appliance usage, no activity periods, and tank filling. Data is collected and transmitted to the cloud at two-second intervals via Wi-Fi networks. The collected water level data are used to train various machine learning (ML) and deep learning (DL) models for disaggregation in filling, appliance use such as geyser, flush, washing machine, and periods of no activity. These models are then evaluated to determine the most effective approach for water disaggregation, with performance assessed using accuracy and F1 score metrics. Out of the tested models, the Long Short- Term Memory (LSTM) model emerged as the best-performing algorithm, achieving an accuracy of 94.09% and an F1 score of 0.88.

Abstract

Large Language Models (LLMs) have demonstrated strong capabilities as autonomous agents through tool use, planning, and decision-making abilities, leading to their widespread adoption across diverse tasks. As task complexity grows, multi-agent LLM systems are increasingly used to collaboratively solve problems. However, safety and security of these multi-agent systems remains largely unexplored. Existing benchmarks and datasets predominantly focus on single-agent settings, failing to capture the unique vulnerabilities of multi-agent dynamics and co-ordination. To address this gap, we introduce textbf{T}hreats and textbf{A}ttacks in textbf{M}ulti-textbf{A}gent textbf{S}ystems (textbf{TAMAS}), a dataset designed to evaluate the robustness and security of multi-agent LLM systems. TAMAS includes five distinct scenarios comprising 250 adversarial instances across five attack types and 163 different normal and attack tools, along with 100 harmless tasks. We assess system performance across 5 backbone LLMs and 3 agent interaction configurations from Autogen framework, highlighting critical challenges and failure modes in current multi-agent deployments. Our findings show that multi-agent systems are highly vulnerable to adversarial attacks, with Impersonation reaching a 73% success rate and other attacks ranging from 27% to 67%, underscoring the need for stronger defenses.

Abstract

Generation Alpha (born 2010-2024) is the first generation fully raised within the digital ecosystem. They exhibit unique linguistic behaviours influenced by rampant online communication and platform-specific cultures. This study examines the rapid evolution of Gen Alpha slang through a comparative analysis of Millennial and Gen Z vernacular. We identify three core linguistic patterns: extreme lexical compression, digital culture-driven semantic shifts and part-of-speech conversion. We construct a comprehensive slang corpus sourced from online platforms and evaluate the performance of four AI translation systems (viz. Google Translate, ChatGPT 4, Gemini 1.0, DeepSeek v3) on over 100 slang terms. Our results reveal significant translation challenges rooted in culturally-bound terms from gaming, meme culture, and mental health discourse. Most errors are the result of inadequate cultural contextualization, with literal translations dominating the error patterns. Our findings highlight the critical limitations in current language models and emphasize the need for adaptive, culturally sensitive and context-aware frameworks that can handle the dynamic lexicon of evolving youth vernacular.