Abstract

Quantum digital signatures ensure unforgeable message authenticity and integrity using quantum principles, offering unconditional security against both classical and quantum attacks. They are crucial for secure communication in high-stakes environments, ensuring trust and long-term protection in the quantum era. Nowadays, the majority of arbitrated quantum signature (AQS) protocols encrypt data qubit by qubit using the quantum one-time pad (QOTP). Despite providing robust data encryption, QOTP is not a good fit for AQS because of its susceptibility to many types of attacks. In this work, we present an efficient AQS protocol to encrypt quantum message ensembles using a distinct encryption technique, the chained controlled unitary operations. In contrast with existing protocols, our approach successfully prevents disavowal and forgery attacks. We hope this contributes to advancing future investigations into the development of AQS protocols .

Abstract

A method for describing, distributing and re-producing specifications of analog IC using AI models, is fulfilled in the ongoing description by (a) creating an AI model to represent the electrical specifications of the analog integrated circuit over a specified range of PVT, input and output loading, and aging conditions,(b) training the AI model with simulation data associated with the analog IC, wherein the simulation inputs include a plurality of instances of PVT (Process, Voltage, Temperature), input/output loading, and aging conditions,(c) electronically enabling peripheral functions with the AI model into an AI model pack, wherein the peripheral functions include a set of computer code modules to extract the AI model, perform user requested operations, calculate specifications of the analog IC on-the-fly and interact with the user, and (d) distributing the encrypted AI model pack to a plurality of users.

Abstract

Virtual Reality (VR) product requires expertise from diverse set of stakeholders. Moving from requirements to design mock-up(s) while building a VR product is an iterative process and requires manual effort. Due to lack of tool support, creating design templates and managing the respective versions turns out to be laborious and difficult. In this paper, we describe VReqDV, a model-driven VR design generation and versioning tool that can address this gap. The tool uses VR meta-model template as a foundation to facilitate a design pipeline. VReqDV can potentially facilitate design generation, design viewing, design versioning, design to require- ments conformity, traceability, and maintenance. It is a step forward in creating a Model-Driven Development pipeline for VR scene design generation. We demonstrate the capabilities of VReqDV using a simple game scene and share our insights for wider adoption by the VR community

Abstract

Drivable Freespace prediction is a fundamental and crucial problem in autonomous driving. Recent works have addressed the problem by representing the entire non-obstacle road regions as the freespace. In contrast our aim is to estimate the driving corridors that are a navigable subset of the entire road region. Unfortunately, existing corridor estimation methods directly assume a BEV centric representation, which is hard to obtain. In contrast, we frame drivable freespace corridor prediction as a pure image perception task, using only monocular camera input. However such a formulation poses several challenges as one doesn’t have the corresponding data for such freespace corridor segments in the image. Consequently, we develop a novel self-supervised approach for freespace sample generation by leveraging future ego trajectories and front-view camera images, making the process of visual corridor estimation dependent on the ego trajectory. We then employ a diffusion process to model the distribution of such segments in the image. However, the existing binary mask based representation for a segment poses many limitations. Therefore, we introduce ContourDiff, a specialized diffusion-based architecture that denoises over contour points rather than relying on binary mask representations, enabling structured and interpretable freespace predictions. We evaluate our approach qualitatively and quantitatively on both nuScenes and CARLA, demonstrating its effectiveness in accurately predicting safe multimodal navigable corridors in the image.

Abstract

Music has long served as a vehicle for political expression, with protest songs playing a central role in articulating dissent and mobilizing collective action. Yet, despite their cultural significance, the linguistic and acoustic signatures that define protest music remain understudied. We present a multimodal computational analysis of protest and non-protest songs spanning multiple decades. Using NLP and audio analysis, we identify the linguistic and musical features that differentiate protest songs. Instead of focusing on classification performance, we treat classification as a diagnostic tool to investigate these features and reveal broader patterns. Protest songs are not just politically charged they are acoustically and linguistically distinct, and we quantify how.

Abstract

SparseLoc is a global localization framework for city-scale scenarios that leverages vision-language foundation models to generate sparse semantic topometric maps in a zero-shot manner. It combines this map representation with a Monte Carlo localization scheme enhanced by a novel late optimization strategy, ensuring improved pose estimation. By constructing compact yet highly discriminative maps and refining localization through a carefully designed optimization schedule, SparseLoc overcomes the limitations of existing topometric localization methods, offering a better solution for global localization at the scale of a city. Our system achieves over a 5× improvement in localization accuracy compared to existing sparse mapping techniques. Despite utilizing only 1/500th of the points of dense mapping methods, it achieves comparable performance, maintaining an average global localization error below 5m and 2° on KITTI Sequences.

Abstract

Negotiation is a fundamental aspect of behavioral economics, which often involves tactics that prioritize self-interest to maximise individual surplus. The role of empathy in this context, however, remains relatively unexplored in literature. This study aims to investigate the potential of empathy as a negotiation tactic, hypothesizing that it may foster a more co-operative environment and result in beneficial outcomes for the individuals. We conducted 2 field experiments in Indian markets, where bargaining is a prevalent practice. Participants were divided into two groups based on their socioeconomic status—higher and lower—while interacting with sellers from a lower socioeconomic background. This setup enabled us to examine the impact of empathy as a negotiation tactic, operationalized through the implicit reasoning "If you were in my place, would you ask for a discount?". Statistical analysis confirmed profound differences in outcomes, underscoring the impact of empathy rationale.

Abstract

This paper explores advanced voltage reference designs with extremely low power consumption, specifically under one microwatt. These designs are crucial for portable electronic systems that rely on minimal power. The paper categorizes these voltage references based on the types of devices used to generate temperature-proportional or complementary signals. It also provides key design examples to illustrate these concepts. Additionally, the paper enhances understanding by conducting a comparative analysis of performance metrics, including power consumption, temperature coefficient, physical size, and resistance to variations in the manufacturing process.

Abstract

This paper presents a dual-loop reference-less Clock and Data Recovery (CDR) architecture implemented in TSMC 28nm CMOS process for PCIe Gen4 application. A novel frequency detector (FD) with a wide frequency acquisition range is presented, which avoids harmonic locking issues and is independent of input transition density. The FD demonstrates rapid locking capabilities, securing synchronization with Pseudo-Random Binary Sequences (PRBS7 and PRBS31) data patterns. The locking time from PCIe Gen1 (2.5Gbps) to PCIe Gen4 (16Gbps) is less than 5us. The CDR achieves a power consumption of less than 2mW with a supply voltage of 0.9V.

Abstract

The heightened sensitivity of circuit behavior to manufacturing processes is surging in sub-nanometer nodes, presenting a formidable challenge for high-dimensional performance modeling. Estimating circuit performance variations resulting from process randomness in upcoming technology nodes aids in implementing appropriate countermeasures to handle them. Addressing this, we introduce a multi-node transfer learning method for predicting the performance of VLSI digital circuits. The proposed method facilitates Zero-shot Learning in future technology nodes based on insights gained from analyzing the circuit’s process-induced behavior in established nodes. The approach is fast, scalable, and robust, leveraging digital standard cell characterization that can be applied to estimate the performance of a wide array of intricate circuits. Experimental results affirm the approach’s exceptional data efficiency, achieving a speed increase of up to 104 times, all the while maintaining superior accuracy compared to traditional simulators.