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@inproceedings{bib_Arch_2025, AUTHOR = {Purini, Venkata Suresh Reddy and Garg, Siddhant and Gaur, Mudit and Bhat, Sankalp S and Mupparapu, Sohan and Ravindran, Arun }, TITLE = {ArchXBench: A Complex Digital Systems Benchmark Suite for LLM Driven RTL Synthesis}, BOOKTITLE = {ACM- Machine Learning for CAD}. YEAR = {2025}}

Modern SoC datapaths include deeply pipelined, domain-specific accelerators, but their RTL implementation and verification are still mostly done by hand. While large language models (LLMs) exhibit advanced code-generation abilities for programming languages like Python, their application to Verilog-like RTL remains in its nascent stage. This is reflected in the simple arithmetic and control circuits currently used to evaluate generative capabilities in existing benchmarks. In this paper, we introduce ArchXBench, a six-level benchmark suite that encompasses complex arithmetic circuits and other advanced digital subsystems drawn from domains such as cryptography, image processing, machine learning, and signal processing. Architecturally, some of these designs are purely combinational, others are multi-cycle or pipelined, and many require hierarchical composition of modules. For each benchmark, we provide a problem description, design specification, and testbench, enabling rapid research in the area of LLM-driven agentic approaches for complex digital systems design. Using zero-shot prompting with Claude Sonnet 4, GPT 4.1, o4-mini-high, and DeepSeek R1 under a pass@5 criterion, we observed that o4-mini-high successfully solves the largest number of benchmarks, 16 out of 30, spanning Levels 1, 2, and 3. From Level 4 onward, however, all models consistently fail, highlighting a clear gap in the capabilities of current state-of-the-art LLMs and prompting/agentic approaches.

@inproceedings{bib_Seer_2024, AUTHOR = {Jain, Siddhant and Jain, Kunal and Ravindran, Arun and Purini, Venkata Suresh Reddy }, TITLE = {Seer: A Framework for Optimizing Traffic Camera Placement and Deep Learning Inference at the Edge for Vehicle Path Reconstruction}, BOOKTITLE = {Symposium on Edge Computing}. YEAR = {2024}}

Integrating traffic cameras with deep learning facilitates real-time multi-camera vehicle path reconstruction, benefiting smart city initiatives such as traffic management and public safety. The high demands on latency, bandwidth, and privacy underscore the necessity of edge computing platforms. However, the continuous operation of compute-intensive deep learning algorithms on round-the-clock camera streams can exceed the compute and power capacities of edge data centers. Therefore, it is critical to strategically deploy and activate camera streams to balance compute demands with performance requirements. Currently, there is a lack of tools to support this planning process. This paper presents Seer, a comprehensive suite of tools and algorithms that aids traffic planners in optimizing traffic camera placement and deep learning model deployment, considering compute and budgetary constraints. Seer encompasses (1) a graph-based algorithm for efficient camera placement incorporating road network topology, (2) a collaborative algorithm for vehicle path reconstruction that enables the use of less accurate but resource-efficient deep learning models, and (3) a scalable traffic simulation framework derived from open-source projects that model city road networks. Evaluations of Seer on two real-world road networks, each with thousands of intersections and simulated vehicle paths, show a 6.3x reduction in compute requirements. This is achieved through a combination of sparse camera deployment and the use of lightweight models, with an average 55% increase in the Hausdorff distance for the path reconstruction algorithm, translating to an absolute increase of 135 to 195 meters.

@inproceedings{bib_Buil_2023, AUTHOR = {Kashera, Vaibhav and Jain, Siddhant and Banerjee, Abhishek and Purini, Venkata Suresh Reddy }, TITLE = {Building Low-Latency Order Books with Hybrid Binary-Linear Search Data Structures on FPGAs}, BOOKTITLE = {International Conference on Field-Programmable Logic and Applications}. YEAR = {2023}}

The popularity of High-Frequency Trading (HFT) or algorithmic trading has surged in the last ten years, largely due to the exponential increase in computing power. However, while software solutions for HFT have become increasingly optimized over time, they are still plagued by network stack, and kernel-user space separation overheads. Order book construction is a crucial step in any HFT system, as it provides a market snapshot on which trading decisions must be based and executed. This paper proposes a simple linear data structure for tracking the order book and a hybrid binary-linear search algorithm to maintain the top bid and ask offers corresponding to marketdepth, on FPGAs. Our approach takes into account that most trading activity occurs on the top of the bid and offer sides. Through design analysis and experimentation, we demonstrate that our simple approach is scalable and practical, outperforming previous methods. Index Terms—HFT, order book, FPGA

@inproceedings{bib_Flow_2023, AUTHOR = {Choudhury, Ziaul Haque and GULATI, ANISH and Purini, Venkata Suresh Reddy }, TITLE = {FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler}, BOOKTITLE = {ACM Transactions on Archietecture and Code Optimization}. YEAR = {2023}}

The exponential performance growth guaranteed by Moore’s law has started to taper in recent years. At the same time, emerging applications like image processing demand heavy computational performance. These factors inevitably lead to the emergence of domain-specific accelerators (DSA) to fill the performance void left by conventional architectures. FPGAs are rapidly evolving towards becoming an alternative to custom ASICs for designing DSAs because of their low power consumption and a higher degree of parallelism. DSA design on FPGAs requires careful calibration of the FPGA compute and memory resources towards achieving optimal throughput. Hardware Descriptive Languages (HDL) like Verilog have been traditionally used to design FPGA hardware. HDLs are not geared towards any domain, and the user has to put in much effort to describe the hardware at the register transfer level. Domain Specific Languages (DSLs) and compilers have been recently used to weave together handwritten HDLs templates targeting a specific domain. Recent efforts have designed DSAs with image-processing DSLs targeting FPGAs. Image computations in the DSL are lowered to pre-existing templates or lower-level languages like HLS-C. This approach requires expensive FPGA re-flashing for every new workload. In contrast to this fixed-function hardware approach, overlays are gaining traction. Overlays are DSAs resembling a processor, which is synthesized and flashed on the FPGA once but is flexible enough to process a broad class of computations through soft reconfiguration. Less work has been reported in the context of image processing overlays. Image processing algorithms vary in size and shape, ranging from simple blurring operations to complex pyramid systems. The primary challenge in designing an image-processing overlay is maintaining flexibility in mapping different algorithms

@inproceedings{bib_A_Cl_2023, AUTHOR = {Jain, Kunal and Sairam, Adapa Kishan and Grover, Kunwar Shaanjeet Singh and Kiran, Santosh Ravi and Purini, Venkata Suresh Reddy }, TITLE = {A Cloud-Fog Architecture for Video Analytics on Large Scale Camera Networks Using Semantic Scene Analysis}, BOOKTITLE = {International Symposium in Cluster, Cloud, and Grid Computing}. YEAR = {2023}}

This paper proposes a scalable distributed video analytics framework that can process thousands of video streams from sources such as CCTV cameras using semantic scene analysis. The main idea is to deploy deep learning pipelines on the fog nodes and generate semantic scene description records (SDRs) of video feeds from the associated CCTV cameras. These SDRs are transmitted to the cloud instead of video frames saving on network bandwidth. Using these SDRs stored on the cloud database, we can answer many complex queries and perform rich video analytics, within extremely low latencies. There is no need to scan and process the video streams again on a per query basis. The software architecture on the fog nodes allows for integrating new deep learning pipelines dynamically into the existing system, thereby supporting novel analytics and queries. We demonstrate the effectiveness of the system by proposing a novel distributed algorithm for real-time vehicle pursuit. The proposed algorithm involves asking multiple spatio-temporal queries in an adaptive fashion to reduce the query processing time and is robust to inaccuracies in the deployed deep learning pipelines and camera failures.

@inproceedings{bib_Acce_2023, AUTHOR = {Kumar, Maram Krishna and Choudhury, Ziaul Haque and Purini, Venkata Suresh Reddy }, TITLE = {Accelerating LU-Decomposition of Arbitrarily Sized Matrices on FPGAs}, BOOKTITLE = {International Symposium on VLSI Design, Automation and Test}. YEAR = {2023}}

In this paper, we design and develop a hardware accelerator for computing the LU decomposition of an input matrix. Our accelerator consists of two simple linear arrays of Processing Engines (PEs), one on each of the two SLR regions of the FPGA. All the computations arising from the block LU decomposition are simplified and scheduled on these two PE arrays. On an Alveo U50 FPGA, our design achieves a peak floating-point performance of 128 GLOPS/s and an average performance of 95 GFLOPS/s. We achieve ≈ 15× speedup on latency compared to an Intel MKL implementation on a 4-core Intel Xeon CPU.

@inproceedings{bib_Hard_2023, AUTHOR = {Yamini, Durgavajjula Shaarada and Ganesh, Mirishkar Sai and Vuppala, Anil Kumar and Purini, Venkata Suresh Reddy }, TITLE = {Hardware Accelerator for Transformer based End-to-End Automatic Speech Recognition System}, BOOKTITLE = {Reconfigurable Architectures Workshop }. YEAR = {2023}}

Hardware accelerators are being designed to offload compute-intensive tasks such as deep neural networks from the CPU to improve the overall performance of an application, specifically on the performance-per-watt metric. Encoder-decoderbased sequence-to-sequence models such as the Transformer model have demonstrated state-of-the-art results in end-to-end automatic speech recognition systems (ASRs). The Transformer model being intensive on memory and computation poses a challenge for an FPGA implementation. This paper proposes an end-to-end architecture to accelerate a Transformer for an ASR system. The host CPU orchestrates the computations from different encoder and decoder stages of the Transformer architecture on the designed hardware accelerator with no necessity for intervening FPGA reconfiguration. The communication latency is hidden by prefetching the weights of the next encoder/decoder block while the current block is being processed. The computation is split across both the Super Logic Regions (SLRs) of the FPGA, mitigating the inter-SLR communication. The proposed design presents an optimal latency, exploiting the available resources. The accelerator design is realized using highlevel synthesis tools and evaluated on an Alveo U-50 FPGA card. The design demonstrates an average speed-up of 32× compared to an Intel Xeon E5-2640 CPU and 8.8× compared to NVIDIA GeForce RTX 3080 Ti Graphics card for a 32-bit floating point single precision model. Index Terms—Automatic speech recognition, Hardware accelerator, Transformer, FPGAs.

@inproceedings{bib_An_F_2022, AUTHOR = {Choudhury, Ziaul Haque and SHRIVASTAVA, SHASHWAT and Purini, Venkata Suresh Reddy }, TITLE = {An FPGA Overlay for CNN Inference with Fine-grained Flexible Parallelism}, BOOKTITLE = {ACM Transactions on Archietecture and Code Optimization}. YEAR = {2022}}

Increasingly, pre-trained convolutional neural networks (CNNs) are being deployed for inference in various computer vision applications, both on the server-side in the data centers and at the edge. CNN inference is a very compute-intensive task. It is a challenge to meet performance metrics such as latency and throughput while optimizing power. Special-purpose ASICs and FPGAs are suitable candidates to meet these power and performance budgets simultaneously. Rapidly evolving CNN architectures involve novel convolution operations such as point convolutions, depth separable convolutions, and so on. This leads to substantial variation in the computational structure across CNNs and layers within a CNN. Because of this, FPGA reconfigurability provides an attractive tradeoff compared to ASICs. FPGA-based hardware designers address the structural variability issue by generating a network-specific accelerator for a single network or a class of networks. However, homogeneous accelerators are network agnostic and often sacrifice throughput and FPGA LUTs for flexibility. In this article, we propose an FPGA overlay for efficient processing of CNNs that can be scaled based on the available compute and memory resources of the FPGA. The overlay is configured on the fly through control words sent by the host on a per-layer basis. Unlike current overlays, our architecture exploits all forms of parallelism inside a convolution operation. A constraint system is employed at the host end to find out the per-layer configuration of the overlay that uses all forms of parallelism in the processing of the layer, resulting in the highest throughput for that layer. We studied the effectiveness of our overlay by using it to process AlexNet, VGG16, YOLO, MobileNet, and ResNet-50 CNNs targeting a Virtex7 and a bigger Ultrascale+VU9P FPGAs. The chosen CNNs have a mix of different types of convolution layers and filter sizes, presenting a good variation in model size and structure. Our accelerator reported a maximum throughput of 1,200 GOps/second on the Virtex7, an improvement of 1.2× to 5× over the recent designs. Also, the reported performance density, measured in giga operations per second per KLUT, is 1.3× to 4× improvement over existing works. Similar speed-up and performance density is also observed for the Ultrascale+VU9P FPGA.

@inproceedings{bib_Accu_2022, AUTHOR = {MAURYA, SHIVANI and Choudhury, Ziaul Haque and Purini, Venkata Suresh Reddy }, TITLE = {Accuracy Configurable FPGA Implementation of Harris Corner Detection}, BOOKTITLE = {Computer Society Annual Symposium on VLSI}. YEAR = {2022}}

Image processing algorithms with intrinsic robust- ness to errors can be approximated for significant resource and energy savings while still meeting the end-user requirements. FPGA-based implementations can increase their suitability for real-time high-speed multimedia applications by leveraging Ap- proximate Computing, an independent field that explores meth- ods to reduce computation costs by allowing minor degradation in intermediate computations. With high volume of pixel level computations, corner detection algorithms such as the Harris Corner Detector (HCD), offer wide range of targets for such strategies. In this paper, we propose an hardware implementation of HCD that relies on approximating the intermediate multi- plication operations using Dynamic Range Unbiased Multiplier (DRUM). With run-time configurable bit-width control of DRUM instances, the visual quality of outputs is shown to depend on the varying accuracy of the corner response. We explore how the errors due to approximate operations propagate to the corner response and attempt to find a threshold that adapts to this inaccuracy across images. The experimental results for implementations on Virtex-7 and Zynq-7000 FPGA devices show that our approximate architecture can match the performance of other HCD implementations while hardly utilizing any on-board memory and signal processing resources. Synthesis results show that the proposed implementation achieves over 60% increase in maximum frequency compared to the base implementation. Finally, the quality metric analysis facilitates the selection of approximate configuration suited to the needs of an application. Index Terms—FPGA, Approximate Computing, DRUM, Image Processing, Harris Corner Detector, Bluespec, Zynq, Virtex

@inproceedings{bib_Syst_2022, AUTHOR = {Prithvi, Velicheti Venkata Sai and Sivani, Pentapati and Purini, Venkata Suresh Reddy }, TITLE = {Systolic Array based FPGA accelerator for Yolov3-tiny}, BOOKTITLE = {High Performance Extreme Computing Conference}. YEAR = {2022}}

FPGAs are increasingly significant for deploying convolutional neural network (CNN) inference models because of performance demands and power constraints in embedded and data centre applications. Object detection and classification are essential tasks in computer vision. You Only Look Once (YOLO) is a very efficient algorithm for object detection and classification with its variant Yolov3-tiny specially designed for embedded applications. This paper presents the FPGA accelerator for multiple precisions (FIXED-8, FIXED-16, FLOAT32) of YoloV3-tiny. We use a homogenous systolic array architecture with a synchronized pipeline adder tree for convolution, allowing it to be scalable for multiple variants of Yolo with a change in host driver. We evaluated the design on Terasic DE5a-Net-DDR4. The Fixed point (FP-8, FP-16) implementations attain a throughput of 57 GOPs/s (> 23%) and 46.16 GOPs/s (> 340 %). We synthesized the first FLOAT32 imnlementation attaining 11.22 GFLOPs/s.

@inproceedings{bib_Pric_2021, AUTHOR = {KHANDELWAL, YASH and DOGRA, ARUSHI and G, KARTHIK and Purini, Venkata Suresh Reddy and Reddy, Puduru V. }, TITLE = {Pricing strategies of an oligopolist in federated cloud markets}, BOOKTITLE = {Journal of Cloud Computing}. YEAR = {2021}}

In this paper, we study how an oligopolist influences the coalition structure in federated cloud markets. Specifically, we use cooperative game theory to model the circumstances under which a cloud provider prefers to join a cloud federation vis-a-vis consider taking a price offer made by an oligopolist. We consider two price offering strategies for an oligopolist: non-adaptive and adaptive. In non-adaptive strategy, an oligopolist makes a price offer to all the cloud providers simultaneously. It can be noted that the oligopolist can buy-out all the cloud providers by making a price offer which is equal to a core allocation and the total price offer made by the oligopolist is equal to the value of the grand coalition. In adaptive strategy, the oligopolist approaches the cloud providers one after another in a sequential manner. We show that by using the adaptive strategy, the oligopolist can buy-out all the cloud providers at a total price offer which is less than that of the non-adaptive strategy

@inproceedings{bib_Mode_2020, AUTHOR = {Palavalasa, Surya Teja and SINGH, YUVRAJ and SINGLA, ADHISH and Purini, Venkata Suresh Reddy and Choppella, Venkatesh }, TITLE = {Model Checking as a Service using Dynamic Resource Scaling }, BOOKTITLE = {International Conference on High Performance Computing}. YEAR = {2020}}

Model checking is now a standard technology for verifying large and complex systems. While there are a range of tools and techniques to verify various properties of a system under consideration, in this work, we restrict our attention to safety checking procedures using explicit state space generation. The necessary hardware resources required in this approach depends on the model complexity and the resulting state transition graph that gets generated. This cannot be estimated apriori. For reasonably realistic models, the available main memory in even high end servers may not be sufficient. Hence, we have to use distributed safety verification approaches on a cluster of nodes. However, the problem of estimating the minimum number of nodes in the cluster for the verification procedure to complete successfully remains unsolved. In this paper, we propose a dynamically scalable model checker using an actor based architecture. Using the proposed approach, an end user can invoke a model checker hosted on a cloud platform in a push button fashion. Our safety verification procedures automatically expands the cluster by requesting more virtual machines from the cloud provider. Finally, the user gets to pay only for the hardware resources he rented for the duration of the verification procedure. We refer to this as Model Checking as Service. We approach this problem by proposing an asynchronous algorithm for safety checking in actor framework. The actor based approach allows for scaling the resources on a need basis and redistributes the work load transparently through state migration. We tested our approach by developing a distributed version of SpinJA model checker using Akka actor framework. We conducted our experiments on Google Cloud Engine (GCE) platform wherein we scale our resources automatically using the GCE API. On large models such as anderson.8 from BEEM benchmark suite, our approach reduced the model checking cost in dollars by 8.6x while reducing the wall clock time to complete the safety checking procedure 5.5x times.

@inproceedings{bib_FPGA_2020, AUTHOR = {SHRIVASTAVA, SHASHWAT and Choudhury, Ziaul Haque and KHANDELWAL, SHASHWAT and Purini, Venkata Suresh Reddy }, TITLE = {FPGA Accelerator for Stereo Vision using Semi-Global Matching through Dependency Relaxation}, BOOKTITLE = {International Conference on Field-Programmable Logic and Applications}. YEAR = {2020}}

In this paper, we propose a fully parallel and pipelined architecture for stereo vision on FPGAs using Semi-Global Matching with Census Transform being used underneath. Further, we extend the above streaming architecture so that multiple pixels can be processed in a data parallel fashion. We expose this data parallelism through dependency relaxation. This establishes a trade-off between accuracy and throughput of the hardware. We tested the proposed architecture on Virtex-7 FPGA using KITTI 2012 and KITTI 2015 datasets. On images of resolution 1280x960, with 64 disparity levels, we are able to run our hardware design at 100 MHz. At this frequency, our design is able to process 322 frames per second which is 1.6 times faster than the state-of-the-art SGM implementation on FPGA. Our system can be scaled to a higher resolution image.

@inproceedings{bib_Acce_2020, AUTHOR = {KHANDELWAL, SHASHWAT and Choudhury, Ziaul Haque and SHRIVASTAVA, SHASHWAT and Purini, Venkata Suresh Reddy }, TITLE = {Accelerating Local Laplacian Filters on FPGAs}, BOOKTITLE = {International Conference on Field-Programmable Logic and Applications}. YEAR = {2020}}

Images when processed using various enhancement techniques often lead to edge degradation and other unwanted artifacts such as halos. These artifacts pose a major problem for photographic applications where they can denude the quality of an image. There is a plethora of edge-aware techniques proposed in the field of image processing. However, these require the application of complex optimization or post-processing methods. Local Laplacian Filtering is an edge-aware image processing technique that involves the construction of simple Gaussian and Laplacian pyramids. This technique can be successfully applied for detail smoothing, detail enhancement, tone mapping and inverse tone mapping of an image while keeping it artifact-free. The problem though with this approach is that it is computationally expensive. Hence, parallelization schemes using multi-core CPUs and GPUs have been proposed. As is well known, they are not power-efficient, and a well-designed hardware architecture on an FPGA can do better on the performance per watt metric. In this paper, we propose a hardware accelerator, which exploits fully the available parallelism in the Local Laplacian Filtering algorithm, while minimizing the utilization of on-chip FPGA resources. On Virtex-7 FPGA, we obtain a 7.5x speed-up to process a 1 MB image when compared to an optimized baseline CPU implementation. To the best of our knowledge, we are not aware of any other hardware accelerators proposed in the research literature for the Local Laplacian Filtering problem.

@inproceedings{bib_Bitw_2020, AUTHOR = {Choudhury, Ziaul Haque and Purini, Venkata Suresh Reddy and Benara, Vinamra and , Uday Bondhugula }, TITLE = {Bitwidth Customization in Image Processing Pipelines using Interval Analysis and SMT Solvers}, BOOKTITLE = {International Conference on Compiler Construction}. YEAR = {2020}}

Unlike CPUs and GPUs, it is possible to use custom fixed-point data types, specified as a tuple (α, β), on FPGAs. The parameters α and β denote the number of integral and fractional bitwidths respectively. The power and area savings while performing arithmetic operations on fixed-point data types are well known to be significant over using floating-point data types. In this paper, we propose a hybrid approach involving interval analysis and SMT solvers, for estimating integral bitwidths at different compute stages, in an image processing pipeline, specified using a domain-specific language (DSL) such as PolyMage. The DSL specification facilitates the compiler analysis to infer the underlying computational structure with ease. We also propose a simple and practical profile-driven greedy heuristic search technique for fractional bitwidth analysis. Using the Horn-Schunck Optical Flow benchmark program, we demonstrate where the conventional range analysis approaches fail, and how we overcome them using the hybrid technique proposed in this paper. The integral bitwidth estimates provided by the hybrid technique on the optical flow benchmark are up to 3x times better when compared with interval analysis.

@inproceedings{bib_An_a_2019, AUTHOR = {Jain, Shalini and Bora, Utpal and Kumar, Prateek and Sinha, Vaibhav B. and Purini, Venkata Suresh Reddy and Upadrasta, Ramakrishna }, TITLE = {An analysis of executable size reduction by LLVM passes}, BOOKTITLE = {CSI Transactions on ICT}. YEAR = {2019}}

The formidable increase in the number of smaller and smarter embedded devices has compelled programmers to develop more and more specialized application programs for these systems. These resource intensive programs that have to be executed on limited memory systems make a strong case for compiler optimizations that reduce the executable size of programs. Standard compilers (like LLVM) offer an out-of-the-box -Oz optimization option—just a series of compiler optimization passes—that is specifically targeted for the reduction of the generated executable size. In this paper, we aim to analyze the effects of optimizations of LLVM compiler on the reduction of executable size. Specifically, we take the size of the executable as a metric and attempt to divide the -Oz series into logical groups and study their individual effects; while also study the effect of their combinations. Our preliminary study over SPEC CPU 2017 benchmarks gives us an insight into the comparative effect of the groups of passes on the executable size. Our work has potential to enable the user to tailor a custom series of passes so as to obtain the desired executable size

@inproceedings{bib_Auto_2018, AUTHOR = {BENARA, VINAMRA and Choudhury, Ziaul Haque and Purini, Venkata Suresh Reddy and BONDHUGULA, UDAY and , }, TITLE = {Automatic Bitwidth Customization for Image Processing Pipelines on FPGAs through a DSL Compiler}, BOOKTITLE = {International Conference on Compiler Construction}. YEAR = {2018}}

High-level synthesis (HLS) has received significant attention in recent years, improving programmability for FPGAs. PolyMage is a domain-specific language (DSL) for image processing pipelines that also has a HLS backend to translate the input DSL into an equivalent circuit that can be synthesized on FPGAs, while leveraging an HLS suite. The data at each stage of a pipeline is stored using a fixed-point data type (alpha,beta) where alpha and beta denote the number of integral and fractional bits. The power and area savings while performing arithmetic operations on fixed-point data type is known to be significant over using floating point. In this paper, we first propose an interval-arithmetic based range analysis (alpha-analysis) algorithm to estimate the number of bits required to store the integral part of the data at each stage of an image processing pipeline. The analysis algorithm uses the homogeneity of pixel signals at each stage to cluster them and perform a combined range analysis. Secondly, we propose a software architecture for easily deploying any kind of interval/affine arithmetic based range analyses in the DSL compiler. Thirdly, we propose a new range analysis technique using Satisfiability Modulo Theory (SMT) solvers, and show that the range estimates obtained through it are very close to the lower bounds obtained through profile-driven analysis.We evaluated our bitwidth analysis algorithms on four image processing benchmarks listed in the order of increasing complexity: Unsharp Mask, Down-Up Sampling, Harris Corner Detection and Horn-Schunck Optical Flow. For example, on Optical Flow, the interval analysis based approach showed an 1.4x and 1.14x improvement on area and power metrics over floating-point representation respectively; whereas the SMT solver based approach showed 2.49x and 1.58x improvement on area and power metrics when compared to interval analysis.

@inproceedings{bib_Synt_2018, AUTHOR = {BENARA, VINAMRA and Choudhury, Ziaul Haque and Purini, Venkata Suresh Reddy and BONDHUGULA, UDAY }, TITLE = {Synthesizing Power and Area Efficient Image Processing Pipelines on FPGAs using Customized Bit-widths}, BOOKTITLE = {Technical Report}. YEAR = {2018}}

High-level synthesis (HLS) has received significant attention in recent years, improving programmability for FPGAs. PolyMage is a domain-specific language (DSL) for image processing pipelines that also has a HLS backend to translate the input DSL into an equivalent circuit that can be synthesized on FPGAs, while leveraging an HLS suite. The data at each stage of a pipeline is stored using a fixed-point data type (alpha,beta) where alpha and beta denote the number of integral and fractional bits. The power and area savings while performing arithmetic operations on fixed-point data type is known to be significant over using floating point. In this paper, we first propose an interval-arithmetic based range analysis (alpha-analysis) algorithm to estimate the number of bits required to store the integral part of the data at each stage of an image processing pipeline. The analysis algorithm uses the homogeneity of pixel signals at each stage to cluster them and perform a combined range analysis. Secondly, we propose a software architecture for easily deploying any kind of interval/affine arithmetic based range analyses in the DSL compiler. Thirdly, we propose a new range analysis technique using Satisfiability Modulo Theory (SMT) solvers, and show that the range estimates obtained through it are very close to the lower bounds obtained through profile-driven analysis.We evaluated our bitwidth analysis algorithms on four image processing benchmarks listed in the order of increasing complexity: Unsharp Mask, Down-Up Sampling, Harris Corner Detection and Horn-Schunck Optical Flow. For example, on Optical Flow, the interval analysis based approach showed an 1.4x and 1.14x improvement on area and power metrics over floating-point representation respectively; whereas the SMT solver based approach showed 2.49x and 1.58x improvement on area and power metrics when compared to interval analysis.

@inproceedings{bib_Clou_2018, AUTHOR = {KHANDELWAL, YASH and Karthik, Ganti and Purini, Venkata Suresh Reddy }, TITLE = {Cloud Federation Formation in Oligopolistic Markets}, BOOKTITLE = {European Conference on Parallel Processing}. YEAR = {2018}}

In this paper, we study how an oligopolist influences the coalition structure in federated cloud markets. Specifically, we use cooperative game theory to model the circumstances under which a cloud provider prefers to join a cloud federation vis-a-vis consider taking a price offer made by an oligopolist

@inproceedings{bib_A_Mu_2018, AUTHOR = {JAIN, SHRENIK and Purini, Venkata Suresh Reddy and Reddy, Puduru V. }, TITLE = {A Multi-Cloud Marketplace Model with Multiple Brokers for IaaS Layer and Generalized Stable Matching}, BOOKTITLE = {International Conference on Utility and Cloud Computing}. YEAR = {2018}}

In this paper, we propose a multi-cloud marketplace model for Infrastructure-as-a-Service (IaaS) layer with multiple cloud providers, intermediate brokers and end users. The brokers service end users subscribed to them by aggregating resources (virtual machines) from cloud providers while maximizing their profits. Similarly cloud providers (producers) allocate their supply of virtual machines to brokers (consumers) so as to maximize their profits. We define the notion of social welfare in this market structure and study two trading schemes. The first scheme involves centralized control which aims at maximizing social welfare but may contain unstable producer-consumer pairs who have an incentive to deviate from the current allocation. The second scheme eliminates such unstable pairs by using a generalization of stable matching algorithm but may lead to sub-optimal social welfare. The stable matching algorithm we proposed in this paper is a particular way of generalizing the original Gale-Shapley algorithm

@inproceedings{bib_Shar_2018, AUTHOR = {GARG, SHALEEN and Kothapalli, Kishore and Purini, Venkata Suresh Reddy }, TITLE = {Share-a-GPU: Providing Simple and Effective Time-Sharing on GPUs}, BOOKTITLE = {INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING, DATA, AND ANALYTICS}. YEAR = {2018}}

Time-sharing, which allows for multiple users to use a shared resource, is an important and fundamental aspect of modern computing systems. However, accelerators such as GPUs, that come without a native operating system do not support time sharing. The inability of accelerators to support time-sharing limits their applicability especially as they are getting deployed in Platform-as-a-Service and Resource-as-a-Service environments. In the former, elastic demands may require preemption where as in the latter, fine-grained economic models of service cost can be supported with time sharing. In this paper, we extend the concept of time sharing to the GPGPU computational space using a cooperative multitasking approach. Our technique is applicable to any GPGPU program written in Compute Unified Device Architecture (CUDA) API provided for C/C++ programming languages. With minimal support from the programmer, our framework incorporates process scheduling, light-weight memory management, and multiGPU support. Our framework provides an abstraction where, in a round-robin manner, every workload can use a GPU(s) over a time quantum exclusively. We demonstrate the applicability of our scheduling framework by running many workloads concurrently in a time sharing manner

@inproceedings{bib_Wave_2018, AUTHOR = {CHATURVEDI, NIKITA and Purini, Venkata Suresh Reddy and Syed, Azeemuddin and Kalyana, M. and Rao, K. Sarjan }, TITLE = {Wavelength Selection to Predict Crude Protein in Sorghum using PLSR}, BOOKTITLE = {Asia Communications and Photonics Conference}. YEAR = {2018}}

We have applied PLSR on NIRS data of Sorghum to select significant wavelengths for Crude-Protein content. Calibration models proposed using single wavelength (1449nm) and a pair (1485nm and 1486nm) give the coefficient of determination (R 2 ) as 0.7928 and 0.8334 respectively.

@inproceedings{bib_Flow_2018, AUTHOR = {Awasthi, Deepak and Syed, Azeemuddin and Purini, Venkata Suresh Reddy and Mazumder, Annesha }, TITLE = {Flow Sensor IoT Node for Wi-Fi Equipped Apartments and Gated Communities}, BOOKTITLE = {Sensors}. YEAR = {2018}}

Water crisis is a major issue across various cities in the world. In recent times, a considerable amount of work has been done on remote monitoring using water flow sensors. In almost all these applications either GSM/GPRS or Zig-Bee has been used for communication. In this work, we propose a resilient water monitoring system using a low power Wi-Fi module. The goal is achieved in three stages: calibration of flow sensor, design of robust IoT node with embedded power management and packaging of the complete system. The aim of calibration is to enhance the linearity range by choosing a suitable meter constant K for the turbine flow sensor. It helps to make the system adaptive to variations in pressure and flow rate. The sensor data is processed and sent to the cloud using power efficient ESP8266 Wi-Fi SoC chip. The packaging of the complete system is done to make it watertight and suitable for usage in …

@inproceedings{bib_GPUS_2017, AUTHOR = {GARG, SHALEEN and Kothapalli, Kishore and Purini, Venkata Suresh Reddy }, TITLE = {GPUScheduler: User Level Preemptive Scheduling for NVIDIA GPUs}, BOOKTITLE = {International Conference on High Performance Computing}. YEAR = {2017}}

In this paper, we present a novel approach to extend the concepts of time sharing and preemption to GPGPU computational space. Our technique is applicable to any batch GPGPU program written in Compute Unified Device Architecture (CUDA) API provided for C/C++ programming languages. It also gives the user freedom to use different scheduling algorithms to schedule the GPGPU programs satisfying specific system level agreements. Our easy-to-use and minimal API makes it very easy for users to run their programs using the GPUScheduler.

@inproceedings{bib_Unsu_2017, AUTHOR = {KATTA, JITENDRA YASASWI BHARADWAJ and KAILASH, G SRI and ANIL, CHILUPURI and Purini, Venkata Suresh Reddy and V, Jawahar C }, TITLE = {Unsupervised learning based approach for plagiarism detection in programming assignments}, BOOKTITLE = {Proceedings of the 10th Innovations in Software Engineering Conference}. YEAR = {2017}}

In this work, we propose a novel hybrid approach for automatic plagiarism detection in programming assignments. Most of the well known plagiarism detectors either employ a text-based approach or use features based on the property of the program at a syntactic level. However, both these approaches succumb to code obfuscation which is a huge obstacle for automatic software plagiarism detection. Our proposed method uses static features extracted from the intermediate representation of a program in a compiler infrastructure such as gcc. We demonstrate the use of unsupervised learning techniques on the extracted feature representations and show that our system is robust to code obfuscation. We test our method on assignments from introductory programming course. The preliminary results show that our system is better when compared to other popular tools like MOSS. For visualizing the local and global …

@inproceedings{bib_Plag_2017, AUTHOR = {KATTA, JITENDRA YASASWI BHARADWAJ and Purini, Venkata Suresh Reddy and V, Jawahar C }, TITLE = {Plagiarism detection in programming assignments using deep features}, BOOKTITLE = {Asian Conference on Pattern Recognition}. YEAR = {2017}}

This paper proposes a method for detecting plagiarism in source-codes using deep features. The embeddings for programs are obtained using a character-level Recurrent Neural Network (char-RNN), which is pre-trained on Linux Kernel source-code. Many popular plagiarism detection tools are based on n-gram techniques at syntactic level. However, these approaches to plagiarism detection fail to capture long term dependencies (non-contiguous interaction) present in the source-code. Contrarily, the proposed deep features capture non-contiguous interaction within n-grams. These are generic in nature and there is no need to fine-tune the char-RNN model again to program submissions from each individual problem-set. Our experiments show the effectiveness of deep features in the task of classifying assignment program submissions as copy, partial-copy and non-copy. Comparing our proposed features with …

@inproceedings{bib_A_Hy_2016, AUTHOR = {Choudhury, Ziaul and Purini, Venkata Suresh Reddy and Krishna, Shiva Rama }, TITLE = {A Hybrid CPU+GPU Working-Set Dictionary}, BOOKTITLE = {International Symposium on Parallel and Distributed Computing}. YEAR = {2016}}

In this paper, we propose a hybrid CPU+GPU data structure, that optimizes search operation for frequently accessed search keys. This is based on the working-set structure due to Badiu et al. [1]. The main idea is to maintain a dynamic set of most frequently accessed keys in the GPU memory and the rest of the keys in the CPU main memory. Further, search queries are processed in batches of size 1K to 16K (K = 210). We measured the query throughput of our data structure using Millions of Queries Processed per Second (MQPS) as a metric, on different key access distributions. On distributions, where some keys are accessed more frequently than others, we achieved 2x higher MQPS when compared to a highly tuned hash map provided by C++ BOOST library, and 1.5x higher MQPS against the B+ tree implementation in the Rodinia GPU benchmark. We further showed the effectiveness of our structure, when it is used to store visited vertices information in breadth-first search traversal of graphs. Here, we achieved 1.2x and 1.5x speedups when compared to the BOOST hash map and the GPU B+ trees respectively.

@inproceedings{bib_Dist_2016, AUTHOR = {SINGLA, ADHISH and Desai, Krishnaji and Purini, Venkata Suresh Reddy and Choppella, Venkatesh }, TITLE = {Distributed safety verification using vertex centric programming model}, BOOKTITLE = {International Symposium on Parallel and Distributed Computing}. YEAR = {2016}}

Software is finding place in deeply embedded systems to large scale distributed systems of cloud service providers such as Amazon and Google. Due to the concurrent and distributed nature of this software, it is hard to test for correctness of such systems in a foolproof manner. Explicit state model checking is an approach in which we build a model of the system and specify the properties it should hold. Then we construct a state transition system from the model and check if it satisfies the specified properties. There are two kinds of properties of interest: safety and liveness. In this paper, we focus our attention on safety verification, which involves checking if the states that are generated in the transition system satisfy some predicate formulae specified in the form of assertions. The main problem here is that the number of states in the transition system grows exponentially with the number of bits required to store the …

@inproceedings{bib_Anuv_2016, AUTHOR = {WANI, NEHAL JAGDISH and MOHANTY, SHARADA PRASANNA and Purini, Venkata Suresh Reddy and Sharma, Dipti Mishra }, TITLE = {Anuvaad Pranaali: A RESTful API for Machine Translation}, BOOKTITLE = {International Conference on Service-Oriented Computing}. YEAR = {2016}}

The current web APIs are end-user centric as they mostly focus on the end results. In this paper, we break this paradigm for one class of scientific workflow problems—machine translation, by designing an API that caters not only to the end users but also allows researchers to find bugs in their systems by exposing the ability to programmatically manipulate the results. Moreover, it follows an easy to replicate workflow based mechanism, which is built on the concept of microservices

@inproceedings{bib_Dyna_2015, AUTHOR = {Kumar, Kapil and Wani, Nehal J. and Purini, Venkata Suresh Reddy }, TITLE = {Dynamic memory and core scaling in virtual machines}, BOOKTITLE = {IEEE International Conference on Cloud Computing}. YEAR = {2015}}

The memory and core requirements of a virtual machine depend on the performance requirements of the applications hosted on it. In this paper, we propose algorithms for dynamic memory and core scaling using a combination of machine learning and feedback control techniques. These algorithms work for sequential and parallel applications such as scientific computations where speedup is the primary performance metric. Then we use these algorithms to address the simultaneous memory and core allocation problem, which is more complex due to possible correlation between these resource requirements. All these algorithms can be applied in a black box fashion without instrumenting the source code of applications.

@inproceedings{bib_Accu_2015, AUTHOR = {MEHTA, ASHUTOSH KUMAR SIKANDAR and MAURYA, SHIVANI and SHARIEF, MOHD NAWAZ and PRANAY, BABU M and Jandhayala, Srivatsava and Purini, Venkata Suresh Reddy }, TITLE = {Accuracy-configurable approximate multiplier with error detection and correction}, BOOKTITLE = {IEEE Region 10 Conference}. YEAR = {2015}}

Real-time multimedia applications which demand very low decoding delays are increasing day-by-day. To address this challenge, in error-resilient applications, many approximate computing architectures for delay critical units have been proposed. In this paper, we propose an architecture for an approximate multiplier, accuracy of which can be configured during the run-time. According to the requirement of the application, the multiplier can be configured to operate in an exact mode or in any of the approximate modes, reducing its decoding delay and the dynamic power consumed. The architecture for the proposed approximate multiplier has been synthesized and simulated using Cadence design tools. Using 16-bit multiplication, it has been demonstrated that, the pass-rate and the propagation delay of the proposed multiplier is comparable or better than most of the published inaccurate multipliers. The proposed approximate multiplier is successfully used in a JPEG conversion application and performances of different accuracy modes are compared.

@inproceedings{bib_Rlc-_2014, AUTHOR = {Kashyap, Sanidhya and DHILLON, JASPAL SINGH and Purini, Venkata Suresh Reddy }, TITLE = {Rlc-a reliable approach to fast and efficient live migration of virtual machines in the clouds}, BOOKTITLE = {IEEE International Conference on Cloud Computing}. YEAR = {2014}}

Today, IaaS cloud providers are dynamically minimizing the cost of data centers operations, while maintaining the Service Level Agreement (SLA). Currently, this is achieved by the live migration capability, which is an advanced state-of-the-art technology of Virtualization. However, existing migration techniques suffer from high network bandwidth utilization, large network data transfer, large migration time as well as the destination's VM failure during migration. In this paper, we propose Reliable Lazy Copy (RLC) - a fast, efficient and a reliable migration technique. RLC provides a reasonable solution for high-efficiency and less disruptive migration scheme by utilizing the three phases of the process migration. For effective network bandwidth utilization and reducing the total migration time, we introduce a learning phase to estimate the writable working set (WWS) prior to the migration, resulting in an almost single time transfer of the pages. Our approach decreases the total data transfer by 1.16 x - 12.21x and the total migration time by a factor of 1.42x - 9.84x against the existing approaches, thus providing a fast and an efficient, reliable VM migration of the VMs in the cloud.

@inproceedings{bib_Virt_2013, AUTHOR = {DHILLON, JASPAL SINGH and Purini, Venkata Suresh Reddy and Kashyap, Sanidhya }, TITLE = {Virtual machine coscheduling: A game theoretic approach}, BOOKTITLE = {IEEE International Conference on Utility and Cloud Computing}. YEAR = {2013}}

When multiple virtual machines (VMs) are co scheduled on the same physical machine, they may undergo a performance degradation. The performance degradation is due to the contention for shared resources like last level cache, hard disk, network bandwidth etc. This can lead to service-level agreement violations and thereby customer dissatisfaction. The classical approach to solve the co scheduling problem involves a central authority which decides a co schedule by solving a constrained optimization problem with an objective function such as average performance degradation. In this paper, we use the theory of stable matchings to provide an alternate game theoretic perspective to the co scheduling problem wherein each VM selfishly tries to minimize its performance degradation. We show that the co scheduling problem can be formulated as a Stable Roommates Problem (SRP). Since certain instances of the SRP do not have any stable matching, we reduce the problem to the Stable Marriages Problem (SMP) via an initial approximation. Gale and Shapley proved that any instance of the SMP has a stable matching and can be found in quadratic time. From a game theoretic perspective, the SMP can be thought of as a matching game which always has a Nash equilibrium. There are distributed algorithms for both the SRP and SMP problems. A VM agent in a distributed algorithm need not reveal its preference list to any other VM. This allows each VM to have a private cost function. A principal advantage of this problem formulation is that it opens up the possibility of applying the rich theory of matching markets from game theory to address various aspects of the VM co scheduling problem such as stability, coalitions and privacy both from a theoretical and practical standpoint. We also propose a new workload characterization technique for a combination of compute and memory intensive workloads. The proposed technique uses a sentinel program and it requires only two runs per workload for characterization. VMs can use this technique in deciding their partner preference ranks in the SRP and SMP problems. The characterization technique has also been used in proposing two new centralized VM co scheduling algorithms whose performance is close to the optimal Blossom algorithm.

@inproceedings{bib_Find_2013, AUTHOR = {Purini, Venkata Suresh Reddy and JAIN, LAKSHYA }, TITLE = {Finding good optimization sequences covering program space}, BOOKTITLE = {ACM Transactions on Archietecture and Code Optimization}. YEAR = {2013}}

The compiler optimizations we enable and the order in which we apply them on a program have a substantial impact on the program execution time. Compilers provide default optimization sequences which can give good program speedup. As the default sequences have to optimize programs with different characteristics, they embed in them multiple subsequences which can optimize different classes of programs. These multiple subsequences may falsely interact with each other and affect the potential program speedup achievable. Instead of searching for a single universally optimal sequence, we can construct a small set of good sequences such that for every program class there exists a near-optimal optimization sequence in the good sequences set. If we can construct such a good sequences set which covers all the program classes in the program space, then we can choose the best sequence for a program by trying all the sequences in the good sequences set. This approach completely circumvents the need to solve the program classification problem. Using a sequence set size of around 10 we got an average speedup up to 14% on PolyBench programs and up to 12% on MiBench programs. Our approach is quite different from either the iterative compilation or machine-learning-based prediction modeling techniques proposed in the literature so far. We use different training and test datasets for cross-validation as against the Leave-One-Out cross-validation technique.

@inproceedings{bib_Inex_2010, AUTHOR = {R, BHARGHAVA and R, ABINESH and Purini, Venkata Suresh Reddy and Regeti, Govindarajulu }, TITLE = {Inexact decision circuits: an application to hamming weight threshold voting}, BOOKTITLE = {International Conference on VLSI Design}. YEAR = {2010}}

In this work, the authors present the idea of inexact decision making, and its application to threshold voting of Hamming weights, used in bus coding schemes, N-modular redundancy (NMR), median filtering, and other pattern matching applications. Decision circuits can be tweaked, to perform in an inexact manner, in order to optimize in terms of delay and power, but still maintaining high system accuracy. One such circuit identified by the authors is the threshold voting of Hamming weights. A majority voter is a special case of this family of circuits. The proposed inexact voter consumes up to 8 times less power than the exact voter, with negligible reduction in system accuracy and performance. The leakage power is also reduced by a factor of 3. The inexact voter allows for a higher frequency of operation, by reducing the critical path delay by a factor of up to 3.4. The results obtained validate the application of inexact decision making, with respect to threshold voters.

@inproceedings{bib_Tran_2010, AUTHOR = {Purini, Venkata Suresh Reddy and R, BHARGHAVA and R, ABINESH and Regeti, Govindarajulu }, TITLE = {Transition Inversion Based Low Power Data Coding Scheme for Buffered Data Transfer}, BOOKTITLE = {International Conference on VLSI Design}. YEAR = {2010}}

In this work the authors propose a data coding protocol that leads to power reduction for block data transfer in off-chip buses. I/O pads driving off-chip buses contribute to a major portion of power dissipation in chips. Also, block data transfer is preferred in most systems like caches, DMA etc. In this proposed work, the prior knowledge of the block of data to be transmitted, when it is stored in the buffer, is exploited in a serial fashion to reduce transitions on every bus line. Statistical analysis shows up to 31.9% reduction in transitions. Benchmark results show that it leads to 29% reduction in power consumption. The technique provides added error detection on the lines of parity bit technique, with similar average error detection capability.