@inproceedings{bib_Grap_2026, AUTHOR = {Joshi, Penta and Shukla, Priyesh }, TITLE = {GraphSynth: Agentic Triton Kernel Synthesis for Non-Standard Attention, Verified Across GPU Generations}, BOOKTITLE = {International Symposium on Microarchitecture Workshops}. YEAR = {2026}}

Agentic kernel-synthesis loops are usually reported by their best number, which says little about whether the loop would survive a change of hardware or an honest verifier. We express GraphSynth, an LLM-driven Triton synthesis workflow for attention variants outside PyTorch’s fused-kernel catalog, as a CHIA dataflow graph: four ChiaFunction stages, exactly one agentic edge, and a correctness gate that is never registered as a tool and therefore cannot be reached by the model that it judges. The loop replays end to end on a machine with no GPU and no credentials in about a minute, and runs for real on a GPU with only the language-model call bypassed. On an A100 the loop verifies all ten operators at 10.82× over eager PyTorch and 3.04× over torch.compile. Re-run on an NVIDIA L40S, which has 1.8× lower bandwidth and a ridge point 2.1× higher, it accepts 9 of 10 at 32.02×, against 11.76× for the same nine on the A100. The speedup nearly triples because the eager baseline is bandwidth-bound and the synthesized kernels are not: averaged over all ten operators the baseline is 1.795× slower on the L40S, against 1.800× predicted from bandwidth alone, while every synthesized kernel got faster. We also report what the first real execution exposed: three defects invisible to any replay, one of them the verifier being right while our own reference was wrong, and the one operator whose kernel does not fit Ada’s shared memory.

@inproceedings{bib_Spar_2026, AUTHOR = {Chakraborty, Rajatabha and Samartha, M P and Pahariya, Vedant and Shukla, Priyesh }, TITLE = {SparseCraft: Agentic Hardware-Software Co-Optimization for Sparse Computing}, BOOKTITLE = {International Symposium on Microarchitecture Workshops}. YEAR = {2026}}

Sparse-accelerator design spaces are usually searched against analytical models, so a design point is admitted on what a model predicts rather than on what the hardware does. SparseCraft closes that gap with a language model inside a closed CHIA loop. In each of 15 iterations the model reads the measured outcome of the previous one and edits the Chisel RTL, the memory configuration and the sparse-kernel schedule of a Gemmini accelerator through MCP tool servers, and no candidate counts until it has been checked for legality, elaborated, simulated cycle-accurately, checked bit-for-bit on every output against a golden reference, and synthesised. The harness turns each measurement into the next work order, a diagnosed bottleneck with matching strategy guidance, the history of tried designs and a score of the model's own prediction, and a second model repairs changes that fail a gate. On a 512×512 GraphChallenge sparse-DNN layer the loop reaches 2.1x fewer cycles, 9.8x less off-chip traffic and 22.8% less area than the block-sparse Gemmini baseline, with 5.61x higher modelled perf/W and 11.8x lower EDP. The levers span three layers: a schedule that keeps the dense operand resident removes 9.8x of the traffic, a zero-gated MAC and a zero-row skip unit that the model wrote in Chisel cut energy, and resizing the memories cuts area.

@inproceedings{bib_Bidi_2026, AUTHOR = {V, Deepak R and Kanawat, Lokendra Singh and Jayadeep, Koya and Shukla, Priyesh }, TITLE = {Bidirectional Quantum Processor Interfacing by a 4-Kelvin Analog Signal Chain for Superconducting Qubit Control and Quantum State Readout}, BOOKTITLE = {Computer Society Annual Symposium on VLSI}. YEAR = {2026}}

This paper presents a comprehensive cryogenic ana- log signal processing architecture designed for superconducting qubit control and quantum state readout operating at 4 Kelvin. The proposed system implements a complete bidirectional signal path bridging room-temperature digital controllers with quantum processors at millikelvin stages. The control path incorporates a Phase-Locked Loop (PLL) for stable local oscillator gener- ation, In-phase/Quadrature (I/Q) modulation for precise qubit gate operations, and a cryogenic power amplifier for signal conditioning. The readout path features a Low Noise Amplifier (LNA) with 14 dB gain and 8-Phase Shift Keying (8-PSK) demodulation for quantum state discrimination. All circuit blocks are designed and validated through SPICE simulations employing cryogenic MOSFET models at 180nm that account for carrier freeze-out, threshold voltage elevation, and enhanced mobility at 4 K. Simulation results demonstrate successful end-to-end signal integrity with I/Q phase error below 2°, image rejection ratio exceeding 35 dB, and symbol error rate below 10−6. This work provides a modular, simulation-validated framework for scalable cryogenic quantum control systems.

@inproceedings{bib_Prob_2026, AUTHOR = {Gottumukkula, Siddarth and Samartha, M P and Pahariya, Vedant and Jain, Priyanshi and Trivedi, Amit Ranjan and Shukla, Priyesh }, TITLE = {ProbSplat: Efficient Probabilistic Hardware for Gaussian Splatting in 3D Scene Reconstruction}, BOOKTITLE = {Computer Society Annual Symposium on VLSI}. YEAR = {2026}}

This paper presents ProbSplat, a Compute-in Memory (CIM)-inspired architecture based on programmable and energy efficient floating-gate inverter columns for probabilistic computing. Improving upon our prior work, ProbSplat programs and stores both means and variances of Gaussian mixture components, and evaluates log-likelihood for gaussian splatting during scene reconstruction with high energy efficiency, suitable for robotics and augmented/virtual reality (AR/VR) at the edge. Our proposed scheme enables independent control of both mean and variance via deterministic adjustment of floating-gate MOSFET threshold voltages, increasing the fidelity of hardware to program probability distributions. The design is simulated in 180nm CMOS on 1.8 V at 50 MHz and achieves mean–variance independence with < 2.4% deviation during 3-D Gaussian mixture modeling. Compared to conventional digital implementations, ProbSplat significantly reduces compute complexity, memory footprint, and power consumption. The scalable framework consumes 18pJ energy per log-likelihood inference with 4-bit precision while operating for 500 mixture functions in a 3-D GMM. Scene reconstruction with ProbSplat’s characteristics gave satisfactory fidelity of 21.99 PSNR (dB) at 8-bit precision.