Bidirectional Quantum Processor Interfacing by a
4-Kelvin Analog Signal Chain for Superconducting
Qubit Control and Quantum State Readout
Deepak R V,Lokendra Singh Kanawat,Koya Jayadeep,Priyesh Shukla
Computer Society Annual Symposium on VLSI, ISVLSI, 2026
@inproceedings{bib_Bidi_2026, AUTHOR = {V, Deepak R and Kanawat, Lokendra Singh and Jayadeep, Koya and Shukla, Priyesh }, TITLE = {Bidirectional Quantum Processor Interfacing by a
4-Kelvin Analog Signal Chain for Superconducting
Qubit Control and Quantum State Readout}, BOOKTITLE = {Computer Society Annual Symposium on VLSI}. YEAR = {2026}}
This paper presents a comprehensive cryogenic ana- log signal processing architecture designed for superconducting qubit control and quantum state readout operating at 4 Kelvin. The proposed system implements a complete bidirectional signal path bridging room-temperature digital controllers with quantum processors at millikelvin stages. The control path incorporates a Phase-Locked Loop (PLL) for stable local oscillator gener- ation, In-phase/Quadrature (I/Q) modulation for precise qubit gate operations, and a cryogenic power amplifier for signal conditioning. The readout path features a Low Noise Amplifier (LNA) with 14 dB gain and 8-Phase Shift Keying (8-PSK) demodulation for quantum state discrimination. All circuit blocks are designed and validated through SPICE simulations employing cryogenic MOSFET models at 180nm that account for carrier freeze-out, threshold voltage elevation, and enhanced mobility at 4 K. Simulation results demonstrate successful end-to-end signal integrity with I/Q phase error below 2°, image rejection ratio exceeding 35 dB, and symbol error rate below 10−6. This work provides a modular, simulation-validated framework for scalable cryogenic quantum control systems.
ProbSplat: Efficient Probabilistic Hardware for
Gaussian Splatting in 3D Scene Reconstruction
Siddarth Gottumukkula,M P Samartha,Vedant Pahariya,Priyanshi Jain,Amit Ranjan Trivedi,Priyesh Shukla
Computer Society Annual Symposium on VLSI, ISVLSI, 2026
@inproceedings{bib_Prob_2026, AUTHOR = {Gottumukkula, Siddarth and Samartha, M P and Pahariya, Vedant and Jain, Priyanshi and Trivedi, Amit Ranjan and Shukla, Priyesh }, TITLE = {ProbSplat: Efficient Probabilistic Hardware for
Gaussian Splatting in 3D Scene Reconstruction}, BOOKTITLE = {Computer Society Annual Symposium on VLSI}. YEAR = {2026}}
This paper presents ProbSplat, a Compute-in Memory (CIM)-inspired architecture based on programmable and energy efficient floating-gate inverter columns for probabilistic computing. Improving upon our prior work, ProbSplat programs and stores both means and variances of Gaussian mixture components, and evaluates log-likelihood for gaussian splatting during scene reconstruction with high energy efficiency, suitable for robotics and augmented/virtual reality (AR/VR) at the edge. Our proposed scheme enables independent control of both mean and variance via deterministic adjustment of floating-gate MOSFET threshold voltages, increasing the fidelity of hardware to program probability distributions. The design is simulated in 180nm CMOS on 1.8 V at 50 MHz and achieves mean–variance independence with < 2.4% deviation during 3-D Gaussian mixture modeling. Compared to conventional digital implementations, ProbSplat significantly reduces compute complexity, memory footprint, and power consumption. The scalable framework consumes 18pJ energy per log-likelihood inference with 4-bit precision while operating for 500 mixture functions in a 3-D GMM. Scene reconstruction with ProbSplat’s characteristics gave satisfactory fidelity of 21.99 PSNR (dB) at 8-bit precision.
