Sandeep Saini

From Msplacements

Url: http://web.iiit.ac.in/~saini_sandeep
E-mail: saini_sandeep@research.iiit.ac.in
Contact No: +91 9177613955

Career objective
Design, development, or research in the areas of Computer Architecture and Compiler Optimization.

Education

  • MS by Research (ECE), IIIT-Hyderabad, June, 2009 (expected);
  • B. Tech. (ECE), IIIT- Hyderabad, June 2008, CGPA 7.41
  • Senior Secondary, Dayanand Model School Jalandhar, 2004, 85.4%
  • Secondary, Dayanand Model School Jalandhar, 2002, 90.2%

Academic & Research Experience

  • Teaching Assistant for Electronic Workshop course, fall 2006.
  • Teaching Assistant for Electronics Circuits course, spring 2006-07.
  • Teaching Assistant for Electronics Circuits course, spring 2007-08.
  • Teaching Assistant for Microprocessor Based System design course, fall 2008- 09.
  • Teaching Assistant for VLSI tools course, spring 2008- 09.
  • Research Assistant at Center for VLSI and Embedded System (CVEST), 2007-08.

Primary Research & MS Thesis

  • Introduction of novel bus coding technique for power and crosstalk reduction in buses.
  • an alternate technique to "Buffer Insertion" for delay, noise, area and power reduction in interconnects.

Publication
[1] J.V.R.Ravindra, Sandeep Saini, M.B.Srinivas, "A Low- Power, High Speed, Asynchronous VLSI Architecture for FIR Filters", 13th IEEE International Symposium Integrated Circuits (ISIC 2007).

[2] Sandeep Saini, Srihari, M.B.Srinivas, “Schmitt Trigger as an Alternative to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects”, Tencon 2009, 23-26 Nov 2009.

[3] Sandeep Saini, A. Mahesh Kumar, Sreehari Veeramachaneni, M.B.Srinivas, "Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects", VLSI design 2010, Banglore.




Academic Achievements & Professional Memberships

  • Won the NTSE Scholarship in year 2002.
  • AIR 1821 (State rank - 49) in AIEEE conducted by CBSE.
  • Named in Dean’s list of merit for the Academic year 2007-08.
  • Organized Robocamp for 3 consecutive years in 06, 07 and 08 at IIIT Hyderabad.

Course work
Low Power CMOS Design, Advance course for HDL, VLSI design, VLSI Tools, Analog and Digital Communications, Information Theory and Coding, Communication Networks, Digital Signal Processing, Microprocessor Based System Design, Digital Logic Design, Control Systems, C Programming , Data structure, Electronics Workshop.



Areas of Interest
Delay reduction, Crosstalk noise avoidance, Low power system design, High-speed circuit design, Robotics.

Computer Skills

  • Assembly Languages  : - 8085/86.
  • Hardware Description Languages : -Verilog, VHDL
  • Internet Technologies Used  : - HIML, flash
  • Programming Languages Used  : - C/, Python.
  • Documentation Tools : - Latex, MS Office MPI , OpenMP.
  • Operating Systems : - GNU/Linux,Windows 95/98/ME/2000/XP/Vista

Projects

  • Delay reduction in on-chip data buses and interconnects. Faculty Advisor: Dr. M.B. Srinivas Abstract: This is final phase of my MS thesis work, which resulted in more than 68% delay reduction in data bus and interconnects. Same project resulted in reduction in area consumption by 87%. By using proposed technique noise reduction was also improved to a large extent. Technologies used: H-Spice, C, Matlab
  • Detecting and correcting the errors at the input of a Digital FIR filter. Faculty Advisor: Dr. M.B. Srinivas Abstract: This is the second Phase of my MS these. The aim is to detect and correct the errors occurring in the High speed dataflow. The proposed technique resulted in 22% more efficiency than existing techniques. Technologies used: Verilog, C
  • A Novel bus coding technique using Binary Representation Canonic Sign Digit. Faculty Advisor: Dr. M.B. Srinivas Abstract: This is the First Phase of my MS thesis. The aim of this project is to implement a new binary number representation to reduce the power dissipated due to switching activity. Simulation resulted in 12% more efficiency than existing technique. Technologies used: Verilog, C
  • Implementation of a virtual machine for MC-6802 microprocessor in C Faculty Advisor: Dr. Ranga Rao Abstract: The aim of this project is to build a virtual machine for the MC-6802 microprocessor in visual studio. This includes all the functionalities like subroutines, interrupts etc. Technologies used: Visual Studio, Data structures
  • Other Projects:
  • 1: Line Follower and Fire Fighter.
  • 2: Down Counter and Alarm
  • 3: Study of Kolmogorov Complexity
  • 4: Maze solving Robot.
  • 5: Verilog implementation of Spread spectrum.
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