Anshul Agarwal

From Msplacements

Url: http://web.iiit.ac.in/~anshulagarwal
E-mail: anshulagarwal@research.iiit.ac.in, anshul.com@gmail.com
Contact No: +91 9885968393

Career objective
Design, development, or research in the areas of Microelectronics and VLSI Design.

Education

  • MS by Research (ECE), IIIT-Hyderabad, December, 2009;
  • B. Tech. (ECE), IIIT- Hyderabad, June 2008, CGPA 7.19
  • Senior Secondary, Central Academy, Kota, Rajasthan, 2003, 81%
  • Secondary, Bishop Conrad, Bareilly, UP, 2001, 81%

Academic & Research Experience

  • Research Assistant, CVEST, May 2008 - December 2009.
  • Teaching Assistant, Design for Testability, Spring 2009.
  • Teaching Assistant, Analog and Digital Circuits, Monsoon 2008.
  • Teaching Assistant, DSP for Computer Scientists, Monsoon 2007.

Primary Research & MS Thesis

Design 0f 8-bit Current Steering DAC with Integrated Power Supply
(Thesis Supervisor: Dr. Satyam Mandavilli)

    This thesis attempts at developing a D/A converter with 8 bit resolution with minimum amount of possible power dissipation. It is thought that power supply needed for the D/A converter should be integrated with the converter itself to provide the required stable characteristics of the power supply instead of depending on the highly stable external power supplies. There are various types of architectures for the design of D/A converter. It is known that the current steering architecture provides high speed and can be realized through integrated circuits easily. Thus the present thesis deals with the analysis and design of a current steering D/A converter with 8 bit resolution with associated, very highly stable power supply.

Design of Variable Voltage Reference using Feedback Control Technique

    Most of the voltage references reported so far are of fixed output voltages, mostly around 1.2V (a bandgap reference circuit). A voltage reference, in which the reference voltage can be varied over a range, 0.7V to 1.4V with high stability is designed. A novel feedback technique is provided in the circuit to obtain a highly stable reference voltage. Through simulations, it has been found that a voltage reference for 0.73V with a temperature stability of about 1 ppm/°C over the range of 0 to 80°C is also possible. Further, there is no start up circuit required as in the case of most of the reference circuits reported.

Publication
[1] Anshul Agarwal, Satyam Mandavilli “Variable Voltage Reference using Feedback Control Technique”, Asia Symposium on Quality Electronic Design (ASQED), Kuala Lampur, Malaysia, 15-16 July, 2009

[2] Anshul Agarwal, Satyam Mandavilli, “A 1 ppm/C Voltage Reference in the Range of 0.73V - 1.4V”, IEEE NEWCAS-TAISA'09, Toulouse, France, 28 June - 1 July, 2009

[3] Anshul Agarwal, Satyam Mandavilli, “Feedback Controlled Variable Voltage Reference using Schottky Diodes”, International Conference on Mechanical and Electronics Engineering (ICMEE), Chennai, India, 24-27 July, 2009


Conferences and Workshops

  • Attended and Presented in IEEE NEWCAS-TAISA'09, Toulouse, France
  • Attended and Presented in IEEE ASQED'09, Kuala Lumpur, Malaysia
  • Attened and Presented in R&D Showcase 2009 at IIIT-Hyderabad, India.
  • Submitted a Research Paper on “Low Power, High Speed Unified Computational Structure For Discrete Transforms Using Systolic Array For Software Defined Radio” in ICASSP 2007.

Course work
Low Power CMOS Design, Advance course for HDL, VLSI design, Digital Logic Design, Microprocessor Based System Design, Digital Signal Processing, Analog and Digital Communications, Information Theory and Coding, Communication Networks, Control Systems, C Programming , Data structure, Electronics Workshop.

Projects

  • Unified Computational Structure for Various Discrete Signal Transforms
    Faculty Advisor: Dr. M.B. Srinivas
    Abstract: In this research project, the aim was to design a unified architecture to compute various discrete transforms, using systolic arrays. Since we can represent any transform in matrix vector product of its coefficients, the proposed design was based on linear systolic array architecture. It consisted of a series of processing elements (PE’s) to compute the product value and a RAM module to store the various transforms coefficients. A new technique was developed to avoid the pre and post processing blocks.
    Technologies used: H-Spice, C, Matlab

  • IEEE 754 standard 32-bit Floating Point Unit
    Faculty Advisor: Dr. M.B. Srinivas
    A 32-bit floating point unit was designed and functionally simulated in Verilog 2001. The FPU architecture complied fully with the IEEE 754 Standard. It supported four arithmetic functions: addition, subtraction, multiplication and division.
    Technologies used: Verilog, FPGA Synthesis, Matlab

  • Bus-Switch Coding: Power dissipation reduction technique
    Faculty Advisor: Dr. Madhu Mutyam
    A dynamic reordering of bus line positions technique in order to minimize the toggling activity on physical bus wires was implemented to drive off-chip buses, where the line capacitance is a dominant factor. The effectiveness of the approach was demonstrated through cycle-accurate simulation of industrial benchmarks in conjunction with post-layout evaluation of speed, power and area overhead.
    Technologies used: C, Matlab

  • Design and simulation of OFDM Signalling
    Faculty Advisor: Dr. Garimella Rama Murthy
    A MATLAB program has been written to investigate Orthogonal Frequency Division Multiplexing (OFDM) communication systems. Single-carrier QAM and multicarrier OFDM are compared to demonstrate the strength of OFDM in multipath channels. Two graphical user interface demonstrations show some of the basic concepts of OFDM.
    Technologies used: Matlab

  • Implementation of a virtual machine for MC-6802 microprocessor in C
    Faculty Advisor: Dr. Ranga Rao
    The aim of this project is to build a virtual machine for the MC-6802 microprocessor in visual studio. This includes all the functionalities like subroutines, interrupts etc.
    Technologies used: Visual Studio, Data structures

  • Other Projects:
    • Design and Analysis of various FULL ADDER architectures.
    • Electronic countdown timer.
    • Series voltage regulator with foldback current.
    • Battery operated Mobile Phone Charger.

Computer Skills

  • Transistor Level Simulators  : - Synopsys H-SPICE, Tanner T-SPICE
  • IC Layout Tools  : - Tanner L-Edit
  • Hardware Description Languages : -Verilog
  • Internet Technologies Used  : - HTML
  • Programming Languages Used  : - C, C++, Python.
  • Other EDA Tools  :- Tanner Tools Pro, P-Spice, Multisim, Active HDL, FPGA Advantage with Leonardo Spectrum
  • Documentation Tools : - Latex, MS Office MPI , OpenMP.
  • Programming Environments : - GNU/GCC, Matlab
  • Operating Systems : - GNU/Linux,Windows 95/98/ME/2000/XP/Vista

Extra Curricular

  • Student Placement Lead for MS by Research 2009 batch, IIIT-Hyderabad.
  • A1.1 Elementary level German language course from Goethe-Zentrum, Hyderabad, India
  • Organizing Member of Felicity’07 Cultural Team (the annual technical-cultural festival at IIIT-Hyderabad).
  • Active member of Photography club.
  • Participated in various cultural events.
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