Publications
Journals
Uma Rajaram, Raja Paul Perinbam, Bharghava, "EHW Architecture for Design of FIR Filters for Adaptive Noise Cancellation",International Journal of Computer Science and Network Security, Vol. 9 No. 1 pp. 41-48.Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas: Efficient Reversible Logic Design of BCD Subtractors. Transactions on Computational Science 3: 99-121 (2009)
NSS Reddy, M. Satyam and Lalkishore, "Cascadable Adiabatic Logic Circuits for Low Power Applications", IET Circuits & Devices, Page 518-526, Volume 2, Issue 6, December 2008.
NSS Reddy, M. Satyam and Lalkishore, "Realization of Adiabatic Four Bit Ripple Counter Using Glitchfree and Cascadable Adiabatic Logic", Technology Spectrum, July, 2008.
J.V.R.Ravindra, M.B.Srinivas, "Model Order Reduction of Linear Time Variant High Speed VLSI Interconnects using Frequency Shift Technique" in International Journal of Electronics, Circuits & Systems (IJECS). Vol. 2 No. 4 Autumn 2008,pp. 205-210.
NSS Reddy, M. Satyam and Lalkishore, "Glitch Free and Cascadable Adiabatic Logic for Low Power Applications", Asian Journal of Scientific Research, March 2008.
E. Srinivasa Rao, M. Satyam and Lalkishore, "Universal Electro Optical Hybrid Logic Gates", International Journal of Semiconductor Physics, Quantum Electronics and Optoelectronics, Volume 11, 2008.
E. Srinivasa Rao, M. Satyam and Lalkishore, Electro Optical Hybrid Logic Gates", International Journal of Semiconductor Physics, Quantum Electronics and Optoelectronics, 2007.
N. Vasantha, M. Satyam, Subba Rao, "Power Optimization in Carry-Save Multiplier by Re-ordering of Vectors" Journal of Computer Society of India, 2007.
J.V.R.Ravindra, M.B.Srinivas, "Delay And Energy Efficient Coding Technique For Capacitive Interconnects" in special issue on Advances in Circuits and Systems for Large Scale Integration in The Journal of Circuits, Systems, and Computers (JCSC). Vol. 16, No. 6 (2007), pp. 929-942.
Conferences
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2010
Arun Bhanu, Mark S. K. Lau, Keck-Voon Ling, Vincent J. Mooney III, Anshul Singh "A More Precise Model of Noise Based CMOS Errors", DELTA 2010,Ho Chi Minh City, January 13-15, 2010
Abinesh R., Bharghava R., Suresh Purini, Govindarajulu, "Transition Inversion based Low Power data coding scheme for Buffered Data Transfer", VLSI Design Conference 2010, Bangalore, India, 3-7 January
Bharghava R., Abinesh R., Suresh Purini, Govindarajulu, "Inexact Decision Circuits: An application to Hamming Weight Threshold Voting", VLSI Design Conference 2010, Bangalore, India, 3-7 January
Sandeep Saini, Srihari Veeramachaneni, A. Mahesh Kumar, Srinivas M.B, "Introduction of an Alternative Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects.", VLSI Design Conference 2010, Bangalore, India, 3-7 January
2009
Mamatha Samson, "Performance Analysis of Dual Vt Asymmetric SRAM-Effect of Process Induced Vt Variations", To appear in the Proceedings of the International Conference on Advances in Computing, Control, and Telecommunication Technologies, December 2009.
Durga Prasad Ressy, Srikanth, P. J. Narayanan, Kishore Kottapally, R. Govindarajulu, "Parallelizing Two Dimensional Convex hull using CUDA and CellBE," in International Conference on High Performance Computing (HiPC) 2009, Students Research Symposium, Cochin, India, 16-19th Dec '09. Sandeep Saini, Srihari, M.B.Srinivas, "Schmitt Trigger as an Alternative to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects", Tencon 2009, 23-26 Nov 2009.
Ronak Bajaj, Saransh Chhabra, Sreehari Veeramachacheni, M. B. Srinivas, "A Novel, Low-Power Array Multiplier Architecture", in 9th International Symposium on Communication and Information Technology (ISCIT) 2009, September 28-30, Songdo - iFEZ ConvensiA, Icheon, Korea.
Akshaykumar Salimath, Satyam Mandavilli, "Simplified 3.3V tolerance circuit for 2.5V I/O design in PCI-X signaling environment," mwscas, pp.491-494, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009
Anshul Agarwal, Satyam Mandavilli, "Feedback Controlled Variable Voltage Reference using Schottky Diodes", International Conference on Mechanical and Electronics Engineering (ICMEE), Chennai, India, 24-27 July, 2009
Anshul Agarwal, Satyam Mandavilli "Variable Voltage Reference using Feedback Control Technique", Asia Symposium on Quality Electronic Design (ASQED), Kuala Lampur, Malaysia, 15-16 July, 2009
Anshul Agarwal, Satyam Mandavilli, "A 1 ppm/C Voltage Reference in the Range of 0.73V - 1.4V", IEEE NEWCAS-TAISA'09, Toulouse, France, 28 June - 1 July, 2009
Mamatha Samson, M.B Srinivas "Analysis of faults of drowsy SRAM cell considering the effect of process variation" VLSI Circuits and Systems-SPIE EUROPE Micro technologies for the New Millennium 4-6 May 2009, Dresden, Germany.
Swathi Ramasahayam, Srinivas M.B. "All Digital Dutycycle Correction Circuit in 90nm based on Mutex", ISVLSI, pp.258-262, 2009 IEEE Computer Society Annual Symposium on VLSI, 2009
Abinesh R., Bharghava R., M.B. Srinivas, "Transition Inversion Based Low Power Data Coding Scheme for Synchronous Serial Communication," ISVLSI, pp.103-108, 2009 IEEE Computer Society Annual Symposium on VLSI, 2009
Anshul Singh, Aman Gupta, Sreehari Veeramachaneni, Srinivas M.B. "A High Performance Unified BCD and Binary Adder/Subtractor", ISVLSI, pp.211-216, 2009 IEEE Computer Society Annual Symposium on VLSI, 2009
Bharghava Rajaram, Abinesh Ramachandran and Srinivas M.B. "Low Power Data Coding Scheme for Synchronous Serial Communication", CSIE 2009 (accepted).
Sreehari Veeramachanen, A. Mahesh Kumar, Venkat Tummala, M.B. Srinivas "Design of a Low Power, Variable-Resolution Flash ADC", VLSI Design Conference 2009, Calcutta.
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2008
Sirisha Nalmela, Govindarajulu Regeti, Chidamber Kulkarni "Balancing coarse-grained pipelined architectures using multiple clock domains on platform FPGA ", IEEE High Performance Reconfigurable Computing Workshop, HiPC08, Bangalore.
NSS Reddy, M. Satyam and Lalkishore, "Minimization of Energy Dissipation in Glitch free and Cascadable Adiabatic Logic Circuits", Proceedings of TENCON 2008, Hyderabad, India
J.V.R.Ravindra, M.B.Srinivas, "Efficient Model Order Reduction Technique using Subspace Iteration Scheme for Linear Time-Varying RLC Circuits" in proceedings of 11th EUROMICRO CONFERENCE on DIGITAL SYSTEM DESIGN Architectures, Methods and Tools (DSD 2008), September 3-5, 2008, University of Parma, Parma, Italy.
Mamatha Samson, M.B Srinivas "Analyzing N-Curve Metrics for Sub-Threshold 65nm CMOS SRAM" proceedings of 8th IEEE Conference on Nano technology, 2008.(Nano"08)pp 25-28,( 2008)18-21 August ,Arlinton, Texas, U.S.A
V.R.Ravindra, M.B.Srinivas, "Reduced-order Modeling of High Speed VLSI Interconnects using Static Superelement Technique for Nano Meter Designs" in the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), June 12-13, 2008, Anaheim, CA, USA. (Co-located with the 45th Design Automation Conference (DAC 2008))
J.V.R.Ravindra, M.B.Srinivas, "Static Superelement Technique based Model Order Reduction for High Speed Nanometer Designs" in The 8th International Conference on Nanotechnology (IEEE NANO), Aug 18-21, 2008, Texas, USA
R. Chang, S. Purini. Amplifying ZPPSAT[1] and the two queries problem. Proceedings of the 23rd Annual IEEE Conference on Computational Complexity, June 2008, University of Maryland, College Park, June 22nd to June 26th, 2008.
J.V.R.Ravindra, M.B.Srinivas, "Generating Reduced Order Models for High Speed VLSI Interconnects using Balancing-Free Square Root Method" in 12th IEEE Workshop on Signal Propagation on Interconnects (SPI 2008). May 12-15, 2008 Avignon, Popes Palace, France. (IEEE Computer Press)
J.V.R.Ravindra, M.B.Srinivas, "Generic Sub-Space Algorithm for Generating Reduced Order Models of Linear Time Varying VLSI Circuits", 18th ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 111-114, May 4-6, 2008.
Mamatha Samson, M.B Srinivas "Read Stability and Write Ability Analysis of Dual-Vt Configurations of a single Cell of an SRAM Array-Effect of Process-Induced Intra-Die Vt Variations" proceedings of 2nd IEEE International Nanoelectronics Conference(INEC08)pp 1015-1019,(2008)24-27 March, Shanghai, China
Mohammed Abid Hussain, Madhu Mutyam: Block remap with turnoff: A variation-tolerant cache design technique. ASP-DAC 2008: 783-788
Abu Saad Papa, Madhu Mutyam: Power management of variation aware chip multiprocessors. ACM Great Lakes Symposium on VLSI 2008: 423-428
T. Venkata Kalyan, Madhu Mutyam: Word-interleaved cache: an energy efficient data cache architecture. ISLPED 2008: 265-270
T. Venkata Kalyan, Madhu Mutyam, P. Vijaya Sankara Rao: Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design. VLSI Design 2008: 235-241
Raghavendra K, Madhu Mutyam: Process Variation Aware Issue Queue Design. DATE 2008: 1438-1443
Avinash Lingamneni, Kirthi Krishna Muntimadugu, Srinivas M B: "Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with In-Built Error Detection", in the proceedings of ISVLSI 2008.
Sreehari Veeramachaneni, Kirthi M. Krishna, Prateek G. V., Subroto S., Bharat S., M. B. Srinivas: A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor. VLSI Design 2008: 547-552
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2007
R.Govindarajulu, M.B.Srinivas, "FPGA based Framework" at Intel Development Forum (IDF) in Bangalore on 21st Aug, 2007 and at Asian Academic Forum in New Delhi during 24 - 26 Oct, 2007.
Shashank Mittal, Md. Zafar Ali Khan, M.B. Srinivas: "A Comparative Study of Different FFT Architectures for Software Defined Radio", International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS-Workshop VII), Samos, Greece, July 16-19, 2007.
N. Vasantha, M. Satyam and Subba Rao, "Technique for Minimizing Power Consumption in Array Multipliers through Input Vector Ordering", IEEE-ICSCN-2007, Anna University, Chennai, 2007.
S. Purini, R. Chang "Bounded queries and the NP machine hypothesis" In Proceedings of the 22nd Annual IEEE Conference on Computational Complexity, pages 52-59, 13-16 June 2007, San Diego, California, USA. IEEE Computer Society 2007.
C.Raghunandan, K.S.Sainarayanan, M.B.Srinivas: "Impact of Process Variations on Bus-Encoding Schemes for Delay Minimization in VLSI Interconnects," in the proceedings of 11th IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS (SPI-2007) May 13-16, 2007, Ruta di Camogli (Genova), Italy.
J.V.R.Ravindra, M.B.Srinivas: "Analytical Crosstalk Model with Inductive Coupling in VLSI Interconnects," in the proceedings of 11th IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS (SPI-2007) May 13-16, 2007, Ruta di Camogli (Genova), Italy
K.S. Sainarayanan, C. Raghunandan," M.B. Srinivas: "Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme", in the proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - 2007, May 9-11, 2007, Porto Alegre, Brazil (Accepted).
Sreehari , Kirthi Krishna M, Lingamneni Avinash , Sreekanth Reddy P, M.B. Srinivas, "Novel High-Speed Redundant Binary to Binary Converter Using Prefix Networks", IEEE International Symposium on Circuits and Systems (ISCAS-2007) New Orleans, USA, May 27-30, 2007, (Accepted).
Sreehari , Lingamneni Avinash, Kirthi Krishna M, M.B.Srinivas, "Novel Architectures for Efficient (m, n) Parallel Counters," In 17th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2007, Stresa-Lago Maggiore, Italy, March 11-13, 2007.
J.V.R.Ravindra, M.B.Srinivas, " Modeling of Full-Wave High Speed On Chip RLC Interconnects using Frequency Shift Technique" in 9th IEEE Electronics Packaging Technology Conference (EPTC 2007), December 10-12, 2007.
J.V.R.Ravindra, M.B.Srinivas, "Model Order Reduction for RLC Interconnects using Response Dependent Condensation" IEEE Region 10 TENCON 2007, October 30- November 2, Taipei, 2007.
K. S. Sainarayanan, C. Raghunandan, J. V. R. Ravindra, M. B. Srinivas, "Bus Coding to Minimize Redundant Bit Transitions" IEEE Region 10 TENCON 2007, October 30- November 2, Taipei, 2007.
J.V.R.Ravindra, Sandeep Saini, Avinash Shukla, M.B.Srinivas, "Sign Extension Based Method Low Power Fast Fourier Transform" in Proceedings of International Conference on SOC (ISSOC 2007), Seoul, Korea, October 17-19, 2007
J.V.R.Ravindra, M.B.Srinivas, "Response Dependent Condensation Based Macromodeling for Linear Time Varying High Speed VLSI Interconnects" in Proceedings of 7th International Symposium on Communications and Information Technologies (ISCIT 2007), October 16-19, 2007.
J.V.R.Ravindra, Sandeep Saini, M.B.Srinivas, " A Low- Power, High Speed, Asynchronous VLSI Architecture for FIR Filters", 13th IEEE International Symposium Integrated Circuits (ISIC 2007), September 26-28, Singapore, 2007. (Accepted)
J.V.R.Ravindra, M.B.Srinivas, "Generating Reduced Order Models using Subspace Iteration for Linear RLC Circuits in Nanometer Designs" in ACM SIGARCH/SIGMICRO 2nd International Conference on Nano-Networks (Nano-Net 2007), September 24-26, 2007.
J.V.R.Ravindra, M.B.Srinivas "Modeling and Analysis of Crosstalk for Distributed RLC Interconnects using Difference Model Approach", ACM SIGDA 20th Symposium on Integrated Circuits and System Design (SBCCI 2007), September 3-6, pp. 207-211, September, 2007, Copacabana, Rio de Janeiro, Brazil.
J.V.R.Ravindra, M.B.Srinivas, "Model Order Reduction Techniques for Non-linear and Time Varying High Speed RLC Interconnects" session on Work in Progress (WiP) 2007, In connection with 10th EUROMICRO CONFERENCE on DIGITAL SYSTEM DESIGN Architectures, Methods and Tools (DSD 2007), pp. 325-330, August 27 - 31, 2007, Lubeck, Germany.
J.V.R.Ravindra, M.B.Srinivas, "A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects", 10th EUROMICRO CONFERENCE on DIGITAL SYSTEM DESIGN Architectures, Methods and Tools (DSD 2007), 18-19, August 27 - 31, 2007, Lubeck, Germany.
K.S.Sainarayanan, J.V.R.Ravindra, C Raghunandan and M B Srinivas, "Coupling Aware Energy-Efficient Data Scrambling On Memory-Processor Interfaces," In 2nd IEEE International Conference on Industrial and Information Systems (ICIIS 2007), 8-11, August 2007, University of Peradeniya, Srilanka.
J.V.R.Ravindra, M.B.Srinivas, "Delay and Skew Analysis of VLSI Interconnects using Difference Model Approach" in Joint Conference on 50th IEEE Mid West Symposium on Circuits and Systems (MWSCAS) and 5th North East Symposium on Circuits and Systems (NEWCAS 2007), August 5-8, 2007, Montreal, Canada.
C. Raghunandan, K.S.Sainarayanan, M.B.Srinivas, "Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise(SSN)," IEEE International Symposium on Circuits and Systems (ISCAS-2007) New Orleans, USA, May 27-30, 2007, (Accepted).
C. Raghunandan, K.S.Sainarayanan, M.B.Srinivas, " Bus-encoding Technique to Reduce Delay, Power and Simultaneous Switching Noise (SSN) in RLC VLSI Interconnects," in the 17th edition of ACM Great Lakes Symposium on VLSI (GLSVLSI-2007) Stresa - Lago Maggiore, Italy March 11-13, 2007.
Sudhakar.M, R.V.Kamala, M.B.Srinivas, "An Unified, Reconfigurable Architecture for Montgomery Multiplication in Finite Fields GF (p) and GF (2n) ", VLSI Design 2007, 6-10 January 2007.
Sreehari , Kirthi Krishna M, Lingamneni Avinash , Sreekanth Reddy. P, M.B.Srinivas, "Novel Architectures for High-speed and Low-power 3-2, 4-2 and 5-2 Compressors," VLSI Design 2007, 6-10 January 2007.
Shashank Mittal, Md. Zafar Ali Khan, M.B. Srinivas," Reconfigurable Architecture for High Speed Computation of Partial DFT for Comb Spectrum Evaluation in Software Defined Radio," International Conference on Wireless and Mobile Communication (ICWMC), France, March 2007 (Accepted).
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2006
J.V.R.Ravindra, M.B.Srinivas, "Delay and Energy Efficient Spatial Coding Technique for Low Power VLSI Applications," in the 6th International Workshop System-on-Chip for Real-Time Applications (IWSOC), Cairo, Egypt, Dec 2006.
C.Raghunandan, K.S.Sainarayanan, M.B.Srinivas, "Encoding with Repeater Insertion for Minimizing Delay in VLSI Interconnects," in the 6th International Workshop System-on-Chip for Real-Time Applications (IWSOC), Cairo, Egypt, Dec 2006.
Sreehari , Lingamneni Avinash, Rajashekhar Reddy M, M.B.Srinivas "Efficient Modulo (2k "1) Binary to Residue Converters" in the 6th International Workshop System-on-Chip for Real-Time Applications (IWSOC), Cairo, Egypt, Dec 2006.
R.V.Kamala, M.B.Srinivas, "Montgomery Modular Inversion with Reduced Number of Multiplications", IEEE TENCON 2006, HongKong, November 14-17 2006.
R.V.Kamala, M.B.Srinivas, "High-Throughput Montgomery Multiplication," IFIP International Conference on Very Large Scale Integration (IEEE/ACM SIGDA Conference), VLSI SOC-2006, Nice, France, 16th Oct - 18th Oct 2006.
R.V.Kamala, Sudhakar M, M.B.Srinivas, "An Efficient Reconfigurable Montgomery Multiplier Architecture for GF (p)", 9th Euro Micro Conference on Digital System Design: Architectures, Methods and Tools (Proceedings published by IEEE Computer Society), Croatia, Europe, 30th Aug - 1st Sept 2006.
R.V.Kamala, M.B.Srinivas, "High-Throughput Montgomery Multiplication", IFIP International Conference on Very Large Scale Integration (IEEE/ACM SIGDA Conference), VLSI SOC-2006, Nice, France, 16th Oct - 18th Oct 2006.
R.V.Kamala, M.B.Srinivas, "Synthesis of a Reversible Bit-Serial GF(2m) Multiplier using a Novel Reversible Gate", 15th International Workshop on Logic and Synthesis(IWLS) (IEEE/ACM SIGDA Workshop), Colorado, USA, 7th June-9th June 2006.
Himanshu Thapliyal and M.B Srinivas et.al, "Modified Montgomery modular multiplication Using 4:2 Compressor And CSA Adder", Proceedings of the Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06) , Kuala Lumpur, Jan 17-19, 2006,pp. 414-417.
K.S.Sainarayanan, J.V.R.Ravindra, Kiran.T.Nath, M.B.Srinivas "Coding for Minimizing Energy in VLSI Interconnects", 18 th International Conference on Microelectronics (ICM) 2006, 16-19 December, King Fahd University of Petroleum and Minerals, Dhahran, Saudi Arabia.
K.S.Sainarayanan, J.V.R.Ravindra, M.B.Srinivas, "Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method " in 3rd International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia.
K.S.Sainarayanan, J.V.R.Ravindra, M.B.Srinivas, "A Novel Coupling Driven Low Power Bus Coding Technique for Minimizing capacitive Crosstalk in VLSI Interconnects", IEEE International Symposium on Circuits and Systems (ISCAS-2006) May 21-24, 2006, Island of Kos, Greece.
K.S.Sainarayanan, J.V.R.Ravindra, M.B.Srinivas "A Low Power Overhead Bus Coding Technique for Minimizing Inductive Crosstalk in VLSI Interconnects" SIGDA 15th International Workshop on Logic & Synthesis (IWLS), June 7-9, 2006, Vail, Colorado, USA.
J.V.R.Ravindra, K.S.Sainarayanan, M.B.Srinivas, "A Novel Low Power Bus Encoding Technique for Minimizing RGB Transitions for LCD Display of Digital Camera", 10th IEEE VLSI Design and Test Symposium 2006 (VDAT-2006) August 9 -12, 2006, Goa, India.
K.S.Sainarayanan, C.Raghunandan, J.V.R.Ravindra, M.B.Srinivas, "Modified Area Efficient Temporal Coding Technique for Delay Minimization in VLSI interconnects," in International SOC design conference (ISOCC) Oct 2006, Seoul, Korea.
K.S.Sainarayanan, C.Raghunandan, J.V.R.Ravindra, M.B.Srinivas, "Efficient Spatial-Temporal Coding Schemes for Minimizing Delay in Interconnects," in IEEE TENCON 2006, 14-17 November 2006, Hong Kong.
Sreehari , Pradeep Yarlagadda, and M. B. Srinivas "A Fully Multiplexer-based Implementation of Redundant Number System" In 15th IEEE/ACM SIGDA International Workshop on Logic & Synthesis (IWLS), June 7-9, 2006, Vail, Colorado, USA
Himanshu Thapliyal, Saurabh Kotiyal and M.B Srinivas, "Novel BCD Adders and their Reversible Logic Implementation for IEEE 754r Format", Proceedings of the 19th IEEE/ACM International Conference on VLSI Design and 5th International Conference on Embedded Systems (VLSI Design 2006), Hyderabad, India, Jan 4-7, 2006,pp. 387-392. IEEE Computer Society Press.
Himanshu Thapliyal, Neela Gopi, Pavan Kumar and M.B Srinivas, "Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture", Proceedings of the 4th ACS/IEEE International Conference on Computer Systems and Applications (AICCSA-06), Dubai, March 2006. IEEE Computer Society Press, pp. 88-92.
Himanshu Thapliyal, M.B Srinivas and Hamid R. Arabnia, "Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format", Proceedings of the 11th International CSI Computer Conference (CSICC'06), Tehran, Jan 24-26, 2006, pp.59-64.
Pallavi Gopineedi, Himanshu Thapliyal and M.B Srinivas, "Novel and efficient 4:2 and 5:2 compressors with minimum number of transistors designed for low-power operations", Proceedings of the International Conference on Embedded Systems and Applications(ESA'06),Las Vegas, U.S.A, June 2006(CSREA Press).
Himanshu Thapliyal and M.B Srinivas, "Novel reversible Multiplier Using Novel Reversible TSG Gate", Proceedings of the 4th ACS/IEEE International Conference on Computer Systems and Applications (AICCSA-06), Dubai, March 2006. IEEE Computer Society Press, pp. 100-103.
Keerthi Laal Kala, M. B. Srinivas, "A Generic Architecture for Intelligent System Hardware", IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS) 2006, 4-7 December 2006, Singapore.
Himanshu Thapliyal and M.B Srinivas, "Reversible Logic Implementation of BCD Subtractor for IEEE 754r Format", Proceedings of the 15th ACM SIGDA International Workshop on Logic & Synthesis (IWLS 2006), Colorado, USA, June 7-9, 2006.
Himanshu Thapliyal and M.B Srinivas, "The New BCD Subtractor and Its Reversible Logic Implementation", Proceedings of the 11th Asia-Pacific Computer Systems Architecture Conference (ACSAC 06), Lecture Notes of Computer Science, vol.4186, pp. 469- 475. Springer-Verlag. Sep 2006.
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2005
Himanshu Thapliyal, Saurabh Kotiyal and M.B Srinivas, "High Speed Hardware Units for Efficient Performance of Modified Montgomery Multiplication", Proceedings of the 8th International Conference on Information Technology (CIT-2005), Bhubaneswar, India, December 20-23, 2005.
Himanshu Thapliyal, R.V.Kamala, M.B.Srinivas, "RSA Encryption/Decryption in Wireless Networks Using an Efficient High Speed Multiplier", in Proc. of IEEE International Conference on Personal Wireless Communications, New Delhi, Jan 2005.
J.V.R.Ravindra, K.S.Sainarayanan, M.B.Srinivas, "A Novel Bus Coding Technique for Low Power Data Transmission" In 9th IEEE VLSI Design and Test Symposium 2005 (VDAT-2005), pp 263-266, August 2005, Bangalore India.
K.S.Sainarayanan, J.V.R.Ravindra, M.B.Srinivas, "An Efficient Power Reduction Technique for Low Power Data I/O Using Gray Code", In IEEE International Conference on Applied Electronics-2005, pp 289-292, September 2005, Pilsen, Czech Republic . J.V.R.Ravindra, K.S.Sainarayanan, M.B.Srinivas, "EDGE: Encoding and Decoding of Generic Data for Minimizing Switched Capacitance and Transition Density for Low Power VLSI Applications", In IEEE International Conference on SOC (ISOCC-05). October 2005, Seoul, Korea.
K.S.Sainarayanan, J.V.R.Ravindra, M.B.Srinivas, "A Novel Deep Sub-micron Low Power Bus Coding Technique", In Proc. of International Association of Science and Technology for Development (IASTED-05), pp 154-159, October 2005, USA.(Published in ACTA Press).
J.V.R.Ravindra, K.S.Sainarayanan, M.B.Srinivas, "An Efficient Power Reduction Technique for Low Power Data I/O for Military Applications", In Proc of 24th Digital Avionics Systems Conference, pp 7.E.3-1-7.E.3.8 October 2005, Washington DC, USA.
Himanshu Thapliyal and M.B Srinivas, "A Novel Time- Area-Power Efficient Single Precision Floating Point Multiplier", Proceedings of the 8th MAPLD Conference (NASA office of Logic Design), Washington D.C, USA, Sep 2005.
K.S.Sainarayanan, J.V.R.Ravindra, M.B.Srinivas, "An Efficient Power Reduction Technique for Low Power Data I/O Using Gray Code" In IEEE International Conference on Applied Electronics (AE-2005), pp 289-292, September 2005, Pilsen, Czech Republic.
Himanshu Thapliyal, Pallavi Gopineedi and M.B Srinivas , "A Low Power Decomposed Hierarchical Multiplier Architecture Embedding Multiplexer Based Full Adders", Proceedings of the 48th IEEE MIDWEST Symposium on Circuits and Systems (MWSCAS 2005), Cincinnati, Ohio, USA, August 7-10, 2005, pp.1485-1488.
Himanshu Thapliyal and M.B Srinivas, "A High Speed and Efficient Method of Elliptic Curve Encryption Using Ancient Indian Vedic Mathematics", Proceedings of the 8th MAPLD Conference (NASA office of Logic Design), Washington D.C, USA, Sep 2005.
Himanshu Thapliyal and M.B Srinivas, "An Efficient Method of Elliptic Curve Encryption Using Ancient Indian Vedic Mathematics", Proceedings of the 48th IEEE MIDWEST Symposium on Circuits and Systems (MWSCAS 2005), Cincinnati, Ohio, USA, August 7-10, 2005, pp. 826-829.
" Himanshu Thapliyal and M.B Srinivas, "Design and Analysis of A Novel Parallel Square and Cube Architecture Based On Ancient Indian Vedic Mathematics", Proceedings of the 48th IEEE MIDWEST Symposium on Circuits and Systems (MWSCAS 2005), Cincinnati, Ohio, USA, August 7-10, 2005, pp.1462-1465.
Himanshu Thapliyal and M.B Srinivas, "VLSI Implementation of RSA Encryption System using Ancient Indian Vedic Mathematics", Proceedings of the Micro technologies of The New Millennium( VLSI Circuits and Systems), Sevilla, Spain, May, 2005,pp. 888- 892.
Himanshu Thapliyal, R.V. Kamala and M.B Srinivas, "RSA Encryption/Decryption in Wireless Networks Using an Efficient High Speed Multiplier", Proceedings of the 2005 IEEE International Conference On Personal Wireless Communications (ICPWC-2005), New Delhi, Jan 2005,pp. 417-419.
Himanshu Thapliyal, M.B Srinivas and Hamid R. Arabnia, "Implementation of A Fast Square In RSA Encryption/Decryption Architecture", Proceedings of the International Conference on Security and Management (SAM-2005), Las Vegas, USA, June 2005, USA, pp. 371-375.
Himanshu Thapliyal, M.B Srinivas and Hamid R. Arabnia, "Faster RSA Encryption/Decryption Architecture Using an Efficient High Speed Overlay Multiplier", Proceedings of the International Conference on Security and Management (SAM-2005), U.S.A, June 2005, pp. 40-44.
Himanshu Thapliyal, M.B Srinivas and Hamid R. Arabnia , "Design And Analysis of A VLSI Based High Performance Low Power Parallel Square Architecture", Proceedings of the International Conference on Algorithmic Mathematics and Computer Science (AMCS-2005), Las Vegas, U.S.A, June 2005, pp. 72-76.
Himanshu Thapliyal, M.B Srinivas and Hamid R. Arabnia , "Design for A Fast And Low Power 2's Complement Multiplier", Proceedings of the International Conference on Computer Design (CDES'05),Las Vegas, U.S.A, June 2005, pp. 165-168.
Himanshu Thapliyal and M.B Srinivas, "The need of DNA computing: reversible design of adders and multipliers using Fredkin gate", Proceedings of SPIE Volume: 6050, pp.271-279.Optomechatronic Micro/Nano Devices and Components, Sapporo, Japan, December 5-7, 2005; Editor(s): Yoshitada Katagiri.
Himanshu Thapliyal and M.B Srinivas, "An extension of Fredkin gate circuits using DNA: reversible logic synthesis of sequential circuits using Fredkin gate", Proceedings of SPIE Volume: 6050, pp.196-202.Optomechatronic Micro/Nano Devices and Components, Sapporo, Japan, December 5-7, 2005; Editor(s): Yoshitada Katagiri.
Himanshu Thapliyal and M.B Srinivas, "Novel Reversible "TSG" Gate and Its Applications for Designing Components of Primitive Reversible/Quantum ALU", Proceedings of the Fifth IEEE International Conference on Information, Communications and Signal Processing (ICICS 2005), Bangkok, Thailand, 6-9 December 2005,pp.1425-1429 .
Himanshu Thapliyal and M.B Srinivas, "Design of Wallace tree multiplier and other components of a quantum ALU using reversible TSG gate", Proceedings of SPIE -- Volume 6264 Quantum Informatics 2005, Yuri I. Ozhigov, Editor, 62640H (May. 31, 2006).
Himanshu Thapliyal, Saurabh Kotiyal and M.B Srinivas, "Reversible Logic Design of 4:2 and 5:2 and Higher Order Compressors", Proceedings of the IEE International SoC Design Conference (ISOCC), Seoul, South Korea, October 20-21, 2005, pp.504-507.
Himanshu Thapliyal and M.B Srinivas, "A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits", Proceedings of the 7th International Symposium on Representations and Methodology of Future Computing Technologies(RM 2005), Tokyo, Japan, September 5-6, 2005.
Himanshu Thapliyal and M.B Srinivas, "Novel Reversible "TSG" Gate and Its Application for Designing Reversible Carry Look Ahead Adder and Other Adder Architectures", Proceedings of the 10th Asia-Pacific Computer Systems Architecture Conference (ACSAC 05), Lecture Notes of Computer Science, vol. 3740, pp. 775-786. Springer-Verlag. Oct 2005.
Himanshu Thapliyal, M.B Srinivas and Mark Zwolinski, "A Beginning in the Reversible Logic Synthesis of Sequential Circuits", Proceedings of the 8th MAPLD Conference (NASA office of Logic Design), Washington D.C, Sep 2005.
Himanshu Thapliyal and M.B Srinivas, "Novel Design and Reversible Logic Synthesis of Multiplexer Based Full Adder and Multipliers", Proceedings of the 48th IEEE MIDWEST Symposium on Circuits and Systems (MWSCAS 2005), Cincinnati, Ohio, USA, August 7-10, 2005, pp.1593-1596.
Himanshu Thapliyal, M.B Srinivas and Hamid R. Arabnia, "A Need of Quantum Computing: Reversible Logic Synthesis of Parallel Binary Adder-Subtractor", Proceedings of the International Conference on Embedded Systems and Applications (ESA'05),Las Vegas, U.S.A, June 2005, pp. 60-67.
Himanshu Thapliyal, M.B Srinivas and Hamid R. Arabnia, "A Reversible Version of 4 x 4 Bit Array Multiplier with Minimum Gates and Garbage Outputs", Proceedings of the International Conference on Embedded Systems and Applications (ESA'05), Las Vegas, U.S.A, June 2005, pp-106-114.
Himanshu Thapliyal, M.B Srinivas and Hamid R. Arabnia, "Reversible Logic Synthesis of Half, Full and Parallel Subtractors", Proceedings of the International Conference on Embedded Systems and Applications (ESA'05), U.S.A, June 2005, pp. 165-172.
Saurabh Kotiyal, Himanshu Thapliyal, M.B Srinivas and Hamid R. Arabnia, "VLSI Implementation of O(n*n) Sorting Algorithms and their Hardware Comparison", Proceedings of the International Conference on Scientific Computing(CSC'05), Las Vegas, U.S.A, June 2005, pp. 74-78.
Himanshu Thapliyal, M.B Srinivas, Rameshwar Rao and Hamid R. Arabnia , "Verilog Coding Style for Efficient Synthesis In FPGA", Proceedings of the International Conference on Computer Design (CDES'05), Las Vegas, U.S.A, June 2005, pp. 85-89.
Keerthi Laal Kala, M. B. Srinivas, "A 32-bit Binary Floating Point Neuro-chip", The First International Conference on Natural Computation and the Second International Conference on Fuzzy Systems and Knowledge Discovery (ICNC-FSKD)27-29 August 2005, China and Springer-Verlag Lecture Notes in Computer Science, Germany.
Yaswanth Narvaneni, M. B. Srinivas "Local Language Support for Handheld Devices" International Conference on Information Technology (ITCC-05) April 04-06, 2005, Las Vegas, Nevada, USA.
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2004
Yaswanth Narvaneni, M.B.Srinivas, Ajay P. Sawhney, "A Student Attendance Monitoring System using Personal Digital Assistants", International Conference on ICT in Education and Development, All India Society for Electronics and Computer Technology 2004", Dec 2004, Bhopal, India (63)
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